参数资料
型号: CM3202-00DE
厂商: ON Semiconductor
文件页数: 3/11页
文件大小: 0K
描述: IC CONVERTER DDR DDR2 WDFN8
产品变化通告: Product Discontinuation 30/Sept/2011
标准包装: 3,000
应用: 转换器,DDR,DDR2
输入电压: 3.1 V ~ 3.6 V
输出数: 2
输出电压: 1.7 V ~ 2.8 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-WDFN 裸露焊盘
供应商设备封装: 8-WDFN(3x3)
包装: 带卷 (TR)
CM3202 ? 00
PACKAGE / PINOUT DIAGRAMS
Pin 1
Marking
Top View
(Pins Down View)
Thermal Pad
Bottom View
(Pins Up View)
VIN
1
8
VDDQ
8
1
NC
VTT
NC
2
3
4
7
6
5
ADJSD
GND
GND
7
6
5
GND
PAD
2
3
4
8 ? Lead WDFN Package
CM3202 ? 00DE
Table 1. PIN DESCRIPTIONS
Lead(s)
1
2
3
4
5
6
7
8
EPad
Name
VIN
NC
VTT
NC
GND
GND
ADJSD
VDDQ
GND
Description
Input supply voltage pin. Bypass with a 220 m F capacitor to GND.
Not internally connected. For better heat flow, connect to GND (exposed pad).
V TT regulator output pin, which is preset to 50% of V DDQ .
Not internally connected. For better heat flow, connect to GND (exposed pad).
Ground pin (analog).
Ground pin (power).
This pin is for V DDQ output voltage adjustment. It is available as long as V DDQ is enabled.
During Manual/Thermal shutdown, it is tightened to GND. The V DDQ output voltage is set
using an external resistor divider connected to ADJSD:
V DDQ = 1.25 V × ((R1 + R2) / R2)
Where R1 is the upper resistor and R2 is the ground ? side resistor. In addition, the ADJSD pin functions as
a Shutdown pin. When ADJSD voltage is higher than 2.7 V (SHDN_H), the circuit is in Shutdown mode.
When ADJSD voltage is below 1.5 V (SHDN_L), both VDDQ and VTT are enabled. A low ? leakage Schottky
diode in series with ADJSD pin is recommended to avoid interference with the voltage adjustment setting.
V DDQ regulator output voltage pin.
The backside exposed pad which serves as the package heatsink. Must be connected to GND.
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