参数资料
| 型号： | CM3202-00DE |
| 厂商： | ON Semiconductor |
| 文件页数： | 7/11页 |
| 文件大小： | 0K |
| 描述： | IC CONVERTER DDR DDR2 WDFN8 |
| 产品变化通告： | Product Discontinuation 30/Sept/2011 |
| 标准包装： | 3,000 |
| 应用： | 转换器，DDR，DDR2 |
| 输入电压： | 3.1 V ~ 3.6 V |
| 输出数： | 2 |
| 输出电压： | 1.7 V ~ 2.8 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-WDFN 裸露焊盘 |
| 供应商设备封装： | 8-WDFN（3x3） |
| 包装： | 带卷 (TR) |
CM3202 ? 00
TYPICAL OPERATING CHARACTERISTICS (Cont’d)
I DDQ
0.5A/div
V DDQ
0.1V/div
VDDQ Transient Response
V IN = 3.3V
TIME (0.2 ms/div)
I TT
0.5A/div
V TT
0.1V/div
VTT Transient Response
V IN
-0.75A
TIME (0.2 ms/div)
APPLICATION INFORMATION
Powering DDR Memory
Double ? Data ? Rate (DDR) memory has provided a huge step in performance for personal computers, servers and graphic
systems. As is apparent in its name, DDR operates at double the data rate of earlier RAM, with two memory accesses per cycle
versus one. DDR SDRAM’s transmit data at both the rising and falling edges of the memory bus clock.
DDR’s use of Stub Series Terminated Logic (SSTL) topology improves noise immunity and power ? supply rejection, while
reducing power dissipation. To achieve this performance improvement, DDR requires more complex power management
architecture than previous RAM technology.
Unlike the conventional DRAM technology, DDR SDRAM uses differential inputs and a reference voltage for all interface
signals. This increases the data bus bandwidth, and lowers the system power consumption. Power consumption is reduced by
lower operating voltage, a lower signal voltage swing associated with Stub Series Terminated Logic (SSTL_2), and by the use
of a termination voltage, V TT . SSTL_2 is an industry standard defined in JEDEC document JESD8 ? 9. SSTL_2 maintains
high ? speed data bus signal integrity by reducing transmission reflections. JEDEC further defines the DDR SDRAM
specification in JESD79C.
DDR memory requires three tightly regulated voltages: V DDQ , V TT , and V REF (see Typical DDR terminations, Class II). In
a typical SSTL_2 receiver, the higher current V DDQ supply voltage is normally 2.5 V with a tolerance of ± 200 mV. The active
bus termination voltage, V TT , is half of V DDQ . V REF is a reference voltage that tracks half of V DDQ, ± 1%, and is compared
with the V TT terminated signal at the receiver. V TT must be within ± 40 mV of V REF
V DD Q
Rs = 25
Line
VTT (=VDDQ/2)
Rt = 25
V DD Q
+
Transmitter
?
Receiver
VREF (=VDDQ/2)
Figure 1. Typical DDR Terminations, Class II
http://onsemi.com
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相关代理商/技术参数 |
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|---|---|
| CM3202-00SM | 制造商:CALMIRCO 制造商全称:California Micro Devices Corp 功能描述:DDR VDDQ and Termination Voltage Regulator |
| CM3202-02DE | 功能描述:线性稳压器 - 标准 VDDQ/VTT Regulator RoHS:否 制造商:STMicroelectronics 输出类型: 极性: 输出电压:1.8 V 输出电流:150 mA 负载调节: 最大输入电压:5.5 V 线路调整率: 最大工作温度:+ 125 C 安装风格:SMD/SMT 封装 / 箱体:SOT-323-5L |
| CM3202-02SM | 功能描述:线性稳压器 - 标准 VDDQ/VTT Regulator P2 Fused RoHS:否 制造商:STMicroelectronics 输出类型: 极性: 输出电压:1.8 V 输出电流:150 mA 负载调节: 最大输入电压:5.5 V 线路调整率: 最大工作温度:+ 125 C 安装风格:SMD/SMT 封装 / 箱体:SOT-323-5L |
| CM3202A3OP | 制造商:CAPELLA 功能描述:High Precision Ambient Light sensor |
| CM3204A3OG | 制造商:CAPELLA 功能描述:5 bit Analog output Ambient light sensor |
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