参数资料
| 型号： | CM3202-00DE |
| 厂商： | ON Semiconductor |
| 文件页数： | 8/11页 |
| 文件大小： | 0K |
| 描述： | IC CONVERTER DDR DDR2 WDFN8 |
| 产品变化通告： | Product Discontinuation 30/Sept/2011 |
| 标准包装： | 3,000 |
| 应用： | 转换器，DDR，DDR2 |
| 输入电压： | 3.1 V ~ 3.6 V |
| 输出数： | 2 |
| 输出电压： | 1.7 V ~ 2.8 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-WDFN 裸露焊盘 |
| 供应商设备封装： | 8-WDFN（3x3） |
| 包装： | 带卷 (TR) |
CM3202 ? 00
APPLICATION INFORMATION (Cont’d)
The VTT power requirement is proportional to the number of data lines and the resistance of the termination resistor, but
does not vary with memory size. In a typical DDR data bus system each data line termination may momentarily consume
16.2 mA to achieve the 405 mV minimum over V TT needed at the receiver:
I terminaton +
405 mV
Rt (25 W )
+ 16.2 mA
A typical 64 Mbyte SSTL ? 2 memory system, with 128 terminated lines, has a worst ? case maximum V TT supply current up
to ± 2.07 A. However, a DDR memory system is dynamic, and the theoretical peak currents only occur for short durations, if
they ever occur at all. These high current peaks can be handled by the V TT external capacitor. In a real memory system, the
continuous average V TT current level in normal operation is less than ± 200 mA.
The VDDQ power supply, in addition to supplying current to the memory banks, could also supply current to controllers
and other circuitry. The current level typically stays within a range of 0.5 A to 1 A, with peaks up to 2 A or more, depending
on memory size and the computing operations being performed.
The tight tracking requirements and the need for V TT to sink, as well as source, current provide unique challenges for
powering DDR SDRAM.
CM3202 ? 00 Regulator
The CM3202 ? 00 dual output linear regulator provides all of the power requirements of DDR memory by combining two
linear regulators into a single TDFN ? 8 package. VDDQ regulator can supply up to 2 A current, and the two ? quadrant V TT
termination regulator has current sink and source capability to ± 2 A. The VDDQ linear regulator uses a PMOS pass element
for a very low dropout voltage, typically 500 mV at a 2 A output. The output voltage of V DDQ can be set by an external voltage
divider. The use of regulators for both the upper and lower side of the VDDQ output allows a fast transient response to any
change of the load, from high current to low current or inversely. The second output, V TT , is regulated at V DDQ /2 by an internal
resistor divider. Same as VDDQ, VTT has the same fast transient response to load change in both directions. The V TT regulator
can source, as well as sink, up to 2 A current. The CM3202 ? 00 is designed for optimal operation from a nominal 3.3 VDC bus,
but can work with VIN as high as 5 V. When operating at higher VIN voltages, attention must be given to the increased package
power dissipation and proportionally increased heat generation.
V REF is typically routed to inputs with high impedance, such as a comparator, with little current draw. An adequate V REF
can be created with a simple voltage divider of precision, matched resistors from V DDQ to ground. A small ceramic bypass
capacitor can also be added for improved noise performance.
Input and Output Capacitors
The CM3202 ? 00 requires that at least a 220 m F electrolytic capacitor be located near the V IN pin for stability and to maintain
the input bus voltage during load transients. An additional 4.7 m F ceramic capacitor between the V IN and the GND, located
as close as possible to those pins, is recommended to ensure stability.
At a minimum of a 220 m F electrolytic capacitor is recommended for the V DDQ output. An additional 4.7 m F ceramic
capacitor between the V DDQ and GND, located very close to those pins, is recommended.
At a minimum of a 220 m F electrolytic capacitor is recommended for the V TT output. This capacitor should have low ESR
to achieve best output transient response. SP or OSCON capacitors provide low ESR at high frequency, and thus are a good
choice. In addition, place a 4.7 m F ceramic capacitor between the V TT pin and GND, located very close to those pins. The total
ESR must be low enough to keep the transient within the V TT window of 40 mV during the transition for source to sink.
An average current step of ± 0.5 A requires:
ESR t
40 mV
1 A
+ 40 m W
Both outputs will remain stable and in regulation even during light or no load conditions.
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相关代理商/技术参数 |
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|---|---|
| CM3202-00SM | 制造商:CALMIRCO 制造商全称:California Micro Devices Corp 功能描述:DDR VDDQ and Termination Voltage Regulator |
| CM3202-02DE | 功能描述:线性稳压器 - 标准 VDDQ/VTT Regulator RoHS:否 制造商:STMicroelectronics 输出类型: 极性: 输出电压:1.8 V 输出电流:150 mA 负载调节: 最大输入电压:5.5 V 线路调整率: 最大工作温度:+ 125 C 安装风格:SMD/SMT 封装 / 箱体:SOT-323-5L |
| CM3202-02SM | 功能描述:线性稳压器 - 标准 VDDQ/VTT Regulator P2 Fused RoHS:否 制造商:STMicroelectronics 输出类型: 极性: 输出电压:1.8 V 输出电流:150 mA 负载调节: 最大输入电压:5.5 V 线路调整率: 最大工作温度:+ 125 C 安装风格:SMD/SMT 封装 / 箱体:SOT-323-5L |
| CM3202A3OP | 制造商:CAPELLA 功能描述:High Precision Ambient Light sensor |
| CM3204A3OG | 制造商:CAPELLA 功能描述:5 bit Analog output Ambient light sensor |
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