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| 型号： | COM20019ILJP |
| 厂商： | STANDARD MICROSYSTEMS CORP |
| 元件分类： | 微控制器/微处理器 |
| 中文描述： | 1 CHANNEL(S), 312.5K bps, LOCAL AREA NETWORK CONTROLLER, PQCC28 |
| 封装： | PLASTIC, LCC-28 |
| 文件页数： | 60/65页 |
| 文件大小： | 386K |
| 代理商： | COM20019ILJP |
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Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
SMSC COM20019I
Page 63
Rev. 09-25-07
DATASHEET
The Pre-Scalar is used to change the data rate. The output clock is selected by CKP3-1 bits in the Set-Up
register. The CKP3-1 bits are changed by writing the Set-Up register from outside the CPU. It's not
synchronized between the CPU and COM20019I. Thus, changing the CKP3-1 timing does not synchronize
with the internal clocks of Pre-Scalar, and changing CKP3-1 may cause spike noise to appear on the
output clock line.
Setting the EF bit will include flip-flops inserted between the Configuration register and Pre-Scalar for
synchronizing the CKP3-1 with Pre-Scalar’s internal clocks.
C)
Shorten The Write Interval Time To The Command Register
The COM20019I limits the write interval time for continuous writing to the Command register. The
minimum interval time is changed by the Data Rate. It's 800 nS at the 312.5 Kbps and 1.6
μS at the
156.25 Kbps. This 1.6
μS is very long for CPU.
Setting the EF bit will change the clock source from OSCK clock (8 times frequency of data rate) to XTAL
clock which is not changed by the data rate, such that the minimum interval time becomes 100 nS.
D)
Eliminate The Write Prohibition Period For The Enable Tx/Rx Commands
The COM20019I has a write prohibition period for writing the Enable Transmit/Receive Commands. This
period is started by the TA or RI bit (Status Reg.) returning to High. This prohibition period is caused by
setting the TA/RI bit with a pulse signal. It is 3.2
μS at 156.25 Kbps. This period may be a problem when
using interrupt processing. The interrupt occurs when the RI bit returns to High. The CPU writes the next
Enable Receive Command to the other page immediately. In this case, the interval time between the
interrupt and writing Command is shorter than 3.2
μS.
Setting the EF bit will cause the TA/RI bit to return to High upon release of the pulse signal for setting the
TA/RI bit, instead of at the start of the pulse. This is illustrated in Figure 10.1.
Tx/Rx completed
TA/RI bit
Setting Pulse
nINTR pin
prohibition period
EF=1
Tx/Rx completed
TA/RI bit
Setting Pulse
nINTR pin
EF=0
Figure 10.1 - EFFECT OF THE EB BIT ON THE TA/RI BIT
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相关代理商/技术参数 |
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| COM20019I-LJP | 制造商:SMSC 制造商全称:SMSC 功能描述:Low Cost ARCNET(ANSI 878.1) Controller with 2k X 8 On-Board RAM |
| COM20019ILJP3V | 功能描述:网络控制器与处理器 IC ARCNET Contrllr RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| COM20019ILJPTR | 功能描述:网络控制器与处理器 IC Arcnet (ANSI 878.1) Controllr 2k x 8 Ram RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| COM20019IP | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| COM20020 | 制造商:SMSC 制造商全称:SMSC 功能描述:COM20020 3.3V ULANC Universal Local Area Network Controller with 2K x 8 On-Board RAM |
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