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参数资料
| 型号： | COP8SGA040N9 |
| 厂商： | National Semiconductor Corporation |
| 英文描述： | 8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART |
| 中文描述： | 8位的CMOS基于ROM和OTP微控制器具有8K到32K的内存，2个比较器和USART |
| 文件页数： | 47/62页 |
| 文件大小： | 913K |
| 代理商： | COP8SGA040N9 |
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14.0 Instruction Set
14.1 INTRODUCTION
This section defines the instruction set of the COP8 Family
members. It contains information about the instruction set
features, addressing modes and types.
14.2 INSTRUCTION FEATURES
The strength of the instruction set is based on the following
features:
Mostly single-byte opcode instructions minimize program
size.
One instruction cycle for the majority of single-byte in-
structions to minimize program execution time.
Many single-byte, multiple function instructions such as
DRSZ.
Three memory mapped pointers: two for register indirect
addressing, and one for the software stack.
Sixteen memory mapped registers that allow an opti-
mized implementation of certain instructions.
Ability to set, reset, and test any individual bit in data
memory address space, including the memory-mapped
I/O ports and registers.
Register-Indirect LOAD and EXCHANGE instructions
with optional automatic post-incrementing or decrement-
ing of the register pointer. This allows for greater effi-
ciency (both in cycle time and program code) in loading,
walking across and processing fields in data memory.
Unique instructions to optimize program size and
throughput efficiency. Some of these instructions are
DRSZ, IFBNE, DCOR, RETSK, VIS and RRC.
14.3 ADDRESSING MODES
The instruction set offers a variety of methods for specifying
memory addresses. Each method is called an addressing
mode. These modes are classified into two categories: op-
erand addressing modes and transfer-of-control addressing
modes. Operand addressing modes are the various meth-
ods of specifying an address for accessing (reading or writ-
ing) data. Transfer-of-control addressing modes are used in
conjunction with jump instructions to control the execution
sequence of the software program.
14.3.1 Operand Addressing Modes
The operand of an instruction specifies what memory loca-
tion is to be affected by that instruction. Several different
operand addressing modes are available, allowing memory
locations to be specified in a variety of ways. An instruction
can specify an address directly by supplying the specific
address, or indirectly by specifying a register pointer. The
contents of the register (or in some cases, two registers)
point to the desired memory location. In the immediate
mode, the data byte to be used is contained in the instruction
itself.
Each addressing mode has its own advantages and disad-
vantages with respect to flexibility, execution speed, and
program compactness. Not all modes are available with all
instructions. The Load (LD) instruction offers the largest
number of addressing modes.
The available addressing modes are:
Direct
Register B or X Indirect
Register
B
or
Decrementing
Immediate
Immediate Short
Indirect from Program Memory
The addressing modes are described below. Each descrip-
tion includes an example of an assembly language instruc-
tion using the described addressing mode.
Direct.
The memory address is specified directly as a byte in
the instruction. In assembly language, the direct address is
written as a numerical value (or a label that has been defined
elsewhere in the program as a numerical value).
Example: Load Accumulator Memory Direct
LD A,05
X
Indirect
with
Post-Incrementing/
Reg/Data
Memory
Accumulator
Memory Location
0005 Hex
Contents
Before
XX Hex
A6 Hex
Contents
After
A6 Hex
A6 Hex
Register B or X Indirect.
The memory address is specified
by the contents of the B Register or X register (pointer
register). In assembly language, the notation [B] or [X] speci-
fies which register serves as the pointer.
Example: Exchange Memory with Accumulator, B Indirect
X A,[B]
Reg/Data
Memory
Accumulator
Memory Location
0005 Hex
B Pointer
Contents
Before
01 Hex
87 Hex
Contents
After
87 Hex
01 Hex
05 Hex
05 Hex
Register
Decrementing.
The relevant memory address is specified
by the contents of the B Register or X register (pointer
register). The pointer register is automatically incremented
or decremented after execution, allowing easy manipulation
of memory blocks with software loops. In assembly lan-
guage, the notation [B+], [B], [X+], or [X] specifies which
register serves as the pointer, and whether the pointer is to
be incremented or decremented.
Example: Exchange Memory with Accumulator, B Indirect
with Post-Increment
X A,[B+]
B
or
X
Indirect
with
Post-Incrementing/
Reg/Data
Memory
Accumulator
Memory Location
0005 Hex
B Pointer
Contents
Before
03 Hex
62 Hex
Contents
After
62 Hex
03 Hex
05 Hex
06 Hex
Intermediate.
The data for the operation follows the instruc-
tion opcode in program memory. In assembly language, the
number sign character (
#
) indicates an immediate operand.
C
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相关代理商/技术参数 |
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| COP8SGA040Q3 | 制造商:NSC 制造商全称:National Semiconductor 功能描述:8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART |
| COP8SGA040Q6 | 制造商:NSC 制造商全称:National Semiconductor 功能描述:8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART |
| COP8SGA040Q7 | 制造商:NSC 制造商全称:National Semiconductor 功能描述:8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART |
| COP8SGA040Q8 | 制造商:NSC 制造商全称:National Semiconductor 功能描述:8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART |
| COP8SGA040Q9 | 制造商:NSC 制造商全称:National Semiconductor 功能描述:8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory, Two Comparators and USART |
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