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参数资料
| 型号： | CS4218-KL |
| 厂商： | CRYSTAL SEMICONDUCTOR CORP |
| 元件分类： | 消费家电 |
| 英文描述： | 16-Bit Stereo Audio Codec |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC44 |
| 封装： | PLASTIC, LCC-44 |
| 文件页数： | 24/44页 |
| 文件大小： | 586K |
| 代理商： | CS4218-KL |
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Serial Control Port (SM4)
Serial Mode 4 separates the audio data from the
control data. Since control data such as gain and
attenuation do not change often, this mode re-
duces the bandwidth needed to support the audio
serial port.
The control information is entered through a
separate port that can be asynchronous to the
audio port and only needs to be updated when
changes in the control data are needed. After a
reset or power down, the control port must be
written once to initialize it if the port will be ac-
cessed to read or write control bits. This initial
write is considered a "dummy" write since the
data is ignored by the codec. A second write is
needed to configure the codec as desired. Then,
the control port only needs to be written to when
a change is desired, or to obtain the status infor-
mation. The control port does not function if the
master clock is not operating. When the control
port is used asynchronously to the audio port,
the noise performance may be slightly degraded
due to the asynchronous digital noise.
Since control data does not need to be accessed
each audio frame, an interrupt pin, MF5:INT, is
included in this mode and will go low when
status has changed. The control port serial data
format is illustrated in Figure 20. The control
port uses one of the multifunction pins as a chip
select line, MF4:CCS, that must be low for en-
tering control data. Although only 23 bits
contain useful data on MF2:CDIN, a minimum
of 31 bits must be written. If more than 31 bits
are written without toggling MF4:CCS, only the
first 31 are recognized. MF1:CDOUT contains
status information that is output on the rising
edge of MF3:CCLK. Status information is re-
peated at the end of the frame, bits 25
through 30, to allow a simple 8-bit shift and
latch register to store the most important status
information using the rising edge of MF4:CCS at
the latch control (see Appendix B).
Interrupt Pin - MF5:INT
Serial Mode 4 defines the multifunction pin
MF5:INT as an open-collector interrupt pin. In
SM4, this pin requires a pullup resistor and will
go low when the ADV bit or DI1 pin change, or
a rising edge on the LCL or RCL bits occurs, or
by exiting an SCLK out of range condition (Er-
ror = 3). The interrupt may be masked by setting
the MASK bit in the control serial data port.
MF5:INT is reset by reading the control serial
port.
1
1
3
MF4:CCS
MF3:CCLK
1
8
9
2
2
1
0
3
Err
0
Version
D
MF2:CDIN
MF1:CDOUT
0
0 0 0
1
Left
A/D Gain
3
0
Right
A/D Gain
3
0
Left
D/A Att.
4
0
Right
D/A Att.
4
0
A
L
R
1 0
Err
A
L
R
D
0 0 0 0 0 0 0 0
D
0
2
3
4
5
6
7
1
1
1
1
1
1
2
2
1
1
2
2
3
2
2
2
2
3
I
I
M
M
Figure 20. SM4 - Control Serial Port
CS4218
24
DS135F1
相关PDF资料 |
PDF描述 |
|---|---|
| CS4218-KQ | 16-Bit Stereo Audio Codec |
| CS4218 | 16-Bit Stereo Audio Codec |
| CS4220 | 24-Bit Stereo Audio Codec with 3V Interface |
| CS4220-KS | IC EEPROM SRL 512X8BIT 8DIP |
| CS4221 | 24-Bit Stereo Audio Codec with 3V Interface |
相关代理商/技术参数 |
参数描述 |
|---|---|
| CS4218-KQ | 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:16-Bit Stereo Audio Codec |
| CS4220 | 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:24-Bit Stereo Audio Codec with 3V Interface |
| CS4220-KS | 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:24-Bit Stereo Audio Codec with 3V Interface |
| CS4220-KSR | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cirrus Logic 功能描述: |
| CS4220-KSZ | 功能描述:接口—CODEC IC 24Bit Str Audio CODEC 3V Intrfc RoHS:否 制造商:Texas Instruments 类型: 分辨率: 转换速率:48 kSPs 接口类型:I2C ADC 数量:2 DAC 数量:4 工作电源电压:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:DSBGA-81 封装:Reel |
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