- 您现在的位置：买卖IC网 > PDF目录380066 > CS4218-KL (CRYSTAL SEMICONDUCTOR CORP) 16-Bit Stereo Audio Codec PDF资料下载
参数资料
| 型号： | CS4218-KL |
| 厂商： | CRYSTAL SEMICONDUCTOR CORP |
| 元件分类： | 消费家电 |
| 英文描述： | 16-Bit Stereo Audio Codec |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC44 |
| 封装： | PLASTIC, LCC-44 |
| 文件页数： | 42/44页 |
| 文件大小： | 586K |
| 代理商： | CS4218-KL |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页当前第42页第43页第44页
To load control data into the codec, three HC597’s are utilized. These are the latches that store the
DSP-sent control data, and shift registers that shift the data into the codec. The codec uses an inverted
SSYNC signal to copy the latches to the shift registers every frame. In this diagram the DSP is as-
sumed to have a data bus bandwidth of at least 24 bits. If the DSP has less than 24-bits, the three
HC597s must be split into two addresses. Since the HC597 internal latches are copied to the shift
registers, the latches continually hold the DSP-sent data; therefore, the DSP only needs to write data to
the latches when a change is desired.
The second section is comprised of an HC595 shift register and latch that is clocked by an inverted
SCLK. The data shifted into the HC595 is transferred to the HC595’s latch by the SSYNC signal. This
HC595 captures the 8 bits prior to the SSYNC signal (which is also MF4:CCS) going high. As shown
in Figure 12, and assuming the MF4:CCS (SSYNC) signal rises at bit 32, the 8-bits prior to MF4:CCS
rising are a copy of all the important status bits. This allows one shift register to capture all the
important information. The interrupt pin cannot reliably be used in this configuration since the interrupt
pin is cleared by reading the control port which occurs asynchronously (every audio frame) with re-
spect to the interrupt occurrence.
The third section is only needed if sample frequencies need to be changed. This section is comprised of
an HC574 octal latch that can be replaced by general purpose port pins if available. This section
controls the sample frequency selection bits: MF6:F1, MF7:F2, MF8:F3 and the RESET pin. A change
in sample rate automatically initiates a calibration cycle.
CS4218
42
DS135F1
相关PDF资料 |
PDF描述 |
|---|---|
| CS4218-KQ | 16-Bit Stereo Audio Codec |
| CS4218 | 16-Bit Stereo Audio Codec |
| CS4220 | 24-Bit Stereo Audio Codec with 3V Interface |
| CS4220-KS | IC EEPROM SRL 512X8BIT 8DIP |
| CS4221 | 24-Bit Stereo Audio Codec with 3V Interface |
相关代理商/技术参数 |
参数描述 |
|---|---|
| CS4218-KQ | 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:16-Bit Stereo Audio Codec |
| CS4220 | 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:24-Bit Stereo Audio Codec with 3V Interface |
| CS4220-KS | 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:24-Bit Stereo Audio Codec with 3V Interface |
| CS4220-KSR | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cirrus Logic 功能描述: |
| CS4220-KSZ | 功能描述:接口—CODEC IC 24Bit Str Audio CODEC 3V Intrfc RoHS:否 制造商:Texas Instruments 类型: 分辨率: 转换速率:48 kSPs 接口类型:I2C ADC 数量:2 DAC 数量:4 工作电源电压:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:DSBGA-81 封装:Reel |
发布紧急采购，3分钟左右您将得到回复。