参数资料
型号: CS4265-DNZR
厂商: Cirrus Logic Inc
文件页数: 26/46页
文件大小: 0K
描述: IC CODEC 24BIT 104DB 32-QFN
标准包装: 6,000
类型: 立体声音频
数据接口: 串行
分辨率(位): 24 b
ADC / DAC 数量: 2 / 2
三角积分调变:
动态范围,标准 ADC / DAC (db): 104 / 104
电压 - 电源,模拟: 3.13 V ~ 5.25 V
电压 - 电源,数字: 3.13 V ~ 5.25 V
工作温度: -40°C ~ 105°C
安装类型: 表面贴装
封装/外壳: 32-QFN
供应商设备封装: 32-QFN 裸露焊盘(5x5)
包装: 带卷 (TR)
配用: 598-1001-ND - BOARD EVAL FOR CS4265 CODEC
32
DS657F3
CS4265
Since the read operation cannot set the MAP, an aborted write operation is used as a preamble. As shown
in Figure 16, the write operation is aborted after the acknowledge for the MAP byte by sending a stop con-
dition. The following pseudocode illustrates an aborted write operation followed by a read operation.
Send start condition.
Send 100111x0 (chip address & write operation).
Receive acknowledge bit.
Send MAP byte.
Receive acknowledge bit.
Send stop condition, aborting write.
Send start condition.
Send 100111x1(chip address & read operation).
Receive acknowledge bit.
Receive byte, contents of selected register.
Send acknowledge bit.
Send stop condition.
4.14
Status Reporting
The CS4265 has comprehensive status reporting capabilities. Many conditions can be reported in the status
register, as listed in the status register descriptions. See “Status - Address 0Dh” on page 43. Each source
may be masked off through mask register bits. In addition, each source may be set to ris ing edge, falling
edge, or level sensitive. Combined with the option of level-sensitive or edge-sensitive modes within the mi-
crocontroller, many different configurations are possible, depending on the needs of the equipment design-
er.
4
5
6
7
24 25
SCL
CHIP ADDRESS (WRITE)
MAP BYTE
DATA
DATA +1
START
ACK
STOP
ACK
1
0 0 1
1
1 AD0 0
SDA
7 6
5 4
3
2 1 0
7
6
1 0
7
6
1 0
7 6
1 0
0
1
2
3
8
9
12
16 17 18 19
10 11
13 14 15
27 28
26
DATA +n
Figure 15. Control Port Timing, IC Write
SCL
CHIP ADDRESS (WRITE)
MAP BYTE
DATA
DATA +1
START
ACK
STOP
ACK
1 0 0
1 1 1 AD0 0
SDA
1
0 0 1 1 1 AD0 1
CHIP ADDRESS (READ)
START
7
6
5 4
3 2 1 0
7
0
7
0
7
0
NO
16
8 9
12 13 14 15
4 5
6 7
0 1
20 21 22 23 24
26 27 28
2 3
10 11
17 18 19
25
ACK
DATA + n
STOP
Figure 16. Control Port Timing, IC Read
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