参数资料
型号: CS42L51-CNZR
厂商: Cirrus Logic Inc
文件页数: 33/43页
文件大小: 0K
描述: IC CODEC LOW-V 24BIT 32-QFP
标准包装: 6,000
类型: 立体声音频
数据接口: PCM 音频接口
分辨率(位): 24 b
ADC / DAC 数量: 2 / 2
三角积分调变:
动态范围,标准 ADC / DAC (db): 98 / 98
电压 - 电源,模拟: 1.8V,2.5V
电压 - 电源,数字: 1.8V,2.5V
工作温度: -10°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 32-QFP
供应商设备封装: 32-QFN 裸露焊盘(5x5)
包装: 管件
配用: 598-1005-ND - BOARD EVAL FOR CS42L51 CODEC
其它名称: Q3956082
DS679F1
39
CS42L51
4.5.1
Slave
LRCK and SCLK are inputs in Slave Mode. The speed of the CODEC is automatically determined based
on the input MCLK/LRCK ratio when the Auto-Detect function is enabled. Certain input clock ratios will
then require an internal divide-by-two of MCLK* using either the MCLKDIV2 bit or the MCLKDIV2 stand-
alone control pin.
Additional clock ratios are allowed when the Auto-Detect function is disabled; but the appropriate speed
mode must be selected using the SPEED[1:0] bits.
4.5.2
Master
LRCK and SCLK are internally derived from the internal MCLK (after the divide, if MCLKDIV2 is enabled).
In Hardware Mode the CODEC operates in single-speed only. In Software Mode, the CODEC operates
in either quarter-, half-, single- or double-speed depending on the setting of the SPEED[1:0] bits.
Auto-Detect
QSM
HSM
SSM
DSM
Disabled
(Software
Mode only)
512, 768, 1024, 1536,
2048, 3072
256, 384, 512, 768,
1024, 1536
128, 192, 256, 384,
512, 768
128, 192, 256, 384
Enabled
1024, 1536, 2048*,
3072*
512, 768, 1024*, 1536*
256, 384, 512*, 768*
128, 192, 256*, 384*
*MCLKDIV2 must be enabled.
Table 3. MCLK/LRCK Ratios
÷ 256
÷ 128
÷ 512
LRCK Output
(Equal to Fs)
Single
Speed
Quarter
Speed
Half
Speed
01
10
11
SCLK Output
÷ 2
÷ 1
0
1
MCLK
MCLKDIV2
÷ 128
00
÷ 4
÷ 2
÷ 8
Single
Speed
Quarter
Speed
Half
Speed
01
10
11
÷ 2
00
Double
Speed
Double
Speed
SPEED[1:0]
Figure 17. Master Mode Timing
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