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参数资料
| 型号： | CS42L51-CNZR |
| 厂商： | Cirrus Logic Inc |
| 文件页数： | 36/43页 |
| 文件大小： | 0K |
| 描述： | IC CODEC LOW-V 24BIT 32-QFP |
| 标准包装： | 6,000 |
| 类型： | 立体声音频 |
| 数据接口： | PCM 音频接口 |
| 分辨率（位）： | 24 b |
| ADC / DAC 数量： | 2 / 2 |
| 三角积分调变： | 是 |
| 动态范围，标准 ADC / DAC (db)： | 98 / 98 |
| 电压 - 电源，模拟： | 1.8V，2.5V |
| 电压 - 电源，数字： | 1.8V，2.5V |
| 工作温度： | -10°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-QFP |
| 供应商设备封装： | 32-QFN 裸露焊盘（5x5） |
| 包装： | 管件 |
| 配用： | 598-1005-ND - BOARD EVAL FOR CS42L51 CODEC |
| 其它名称： | Q3956082 |
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DS679F1
41
CS42L51
4.7
Initialization
The initialization and Power-Down sequence flowchart is shown in Figure 22 on page 42. The CODEC en-
ters a Power-Down state upon initial power-up. The interpolation and decimation filters, delta-sigma modu-
lators and control port registers are reset. The internal voltage reference, multi-bit DAC and ADC and
switched-capacitor low-pass filters are powered down.
The device will remain in the Power-Down state until the RESET pin is brought high. The control port is ac-
cessible once RESET is high and the desired register settings can be loaded per the interface descriptions
in “Software Mode” on page 43. If a valid write sequence to the control port is not made within approximately
10 ms, the CODEC will enter Hardware Mode.
Once MCLK is valid, the quiescent voltage, VQ, and the internal voltage references, DAC_FILT+ and
ADC_FILT+ will begin powering up to normal operation. The charge pump slowly powers up and charges
the capacitors. Power is then applied to the headphone amplifiers and switched-capacitor filters, and the an-
alog/digital outputs enter a muted state. Once LRCK is valid, MCLK occurrences are counted over one LRCK
period to determine the MCLK/LRCK frequency ratio and normal operation begins.
4.8
Recommended Power-Up Sequence
1.
Hold RESET low until the power supplies are stable.
2.
Bring RESET high. After approximately 10 ms, the device will enter Hardware Mode.
3.
For Software Mode operation, set the PDN bit to ‘1’b in under 10 ms. This will place the device in “stand-
by”.
4.
Load the desired register settings while keeping the PDN bit set to ‘1’b.
5.
Start MCLK to the appropriate frequency, as discussed in Section 4.5.
6.
Set the PDN bit to ‘0’b.
7.
Apply LRCK,SCLK and SDIN for normal operation to begin.
8.
Bring RESET low if the analog or digital supplies drop below the recommended operating condition to
prevent power glitch related issues.
LRCK
SCLK
MS B
LS B
MS B
LS B
L e ft C han ne l
R ig h t C h an n e l
SDIN
MSB
AOUTA / AINxA
AOUTB / AINxB
Figure 20. Left-Justified Format
LRCK
SCLK
MS B
LS B
MS B
LS B
Left C han ne l
R ig h t C han ne l
SDIN
AOUTA
AOUTB
Figure 21. Right-Justified Format (DAC only)
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相关代理商/技术参数 |
参数描述 |
|---|---|
| CS42L51-DNZ | 功能描述:接口—CODEC LV Stereo Codec F/ Digital Audio Apps RoHS:否 制造商:Texas Instruments 类型: 分辨率: 转换速率:48 kSPs 接口类型:I2C ADC 数量:2 DAC 数量:4 工作电源电压:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:DSBGA-81 封装:Reel |
| CS42L51-DNZR | 功能描述:接口—CODEC IC LV Stereo Codec F Digital Audio Apps RoHS:否 制造商:Texas Instruments 类型: 分辨率: 转换速率:48 kSPs 接口类型:I2C ADC 数量:2 DAC 数量:4 工作电源电压:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:DSBGA-81 封装:Reel |
| CS42L52 | 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:2Low-power, Stereo CODEC w/ Headphone & Speaker Amps |
| CS42L52_08 | 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:2Low-power, Stereo CODEC w/ Headphone & Speaker Amps |
| CS42L52-CNZ | 功能描述:接口—CODEC Low Power Stereo CODEC w/ HP+Spkr Amp RoHS:否 制造商:Texas Instruments 类型: 分辨率: 转换速率:48 kSPs 接口类型:I2C ADC 数量:2 DAC 数量:4 工作电源电压:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:DSBGA-81 封装:Reel |
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