参数资料
型号: CS4351-DZZ
厂商: Cirrus Logic Inc
文件页数: 22/37页
文件大小: 0K
描述: IC DAC STER 112DB 192KHZ 20TSSOP
标准包装: 74
位数: 24
数据接口: 串行
转换器数目: 2
电压电源: 模拟和数字
功率耗散(最大): 354mW
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 20-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 20-TSSOP
包装: 托盘
输出数目和类型: 2 电压,单极
采样率(每秒): 192k
配用: 598-1152-ND - BOARD EVAL FOR CS4351 DAC
DS566F1
29
CS4351
Soft Ramp and Zero Cross
Soft Ramp and Zero Cross Enable dictate that signal level changes, either by attenuation changes or mut-
ing, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will
occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample
rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored
and implemented for each channel.
6.6.2
Soft Volume Ramp-Up After Error (RMP_UP) Bit 5
Function:
When set to 1 (default), an un-mute will be performed after executing a filter mode change, after a
LRCK/MCLK ratio change or error, and after changing the Functional Mode. This un-mute is affected, sim-
ilar to attenuation changes, by the Soft and Zero Cross bits in the Volume and Mixing Control register.
When set to 0, an immediate un-mute is performed in these instances.
Note:
For best results, it is recommended this feature be used in conjunction with the RMP_DN bit.
6.6.3
Soft Ramp-Down Before Filter Mode Change (RMP_DN) Bit 4
Function:
When set to 1 (default), a mute will be performed prior to executing a filter mode change. This mute is
affected, similar to attenuation changes, by the Soft and Zero Cross bits in the Volume and Mixing Control
register.
When set to 0, an immediate mute is performed prior to executing a filter mode change.
Note:
For best results, it is recommended that this feature be used in conjunction with the RMP_UP bit.
6.6.4
Interpolation Filter Select (FILT_SEL) Bit 2
Function:
When set to 0 (default), the Interpolation Filter has a fast roll off.
When set to 1, the Interpolation Filter has a slow roll off.
The specifications for each filter can be found in the “Combined Interpolation & On-Chip Analog Filter Re-
sponse” section on page 8, and response plots can be found in Figures 15 to 36.
6.7
Misc Control - Register 08h
7
6
5
432
10
PDN
CPEN
FREEZE
Reserved
1
0
000
00
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