参数资料
型号: CS4351-DZZ
厂商: Cirrus Logic Inc
文件页数: 8/37页
文件大小: 0K
描述: IC DAC STER 112DB 192KHZ 20TSSOP
标准包装: 74
位数: 24
数据接口: 串行
转换器数目: 2
电压电源: 模拟和数字
功率耗散(最大): 354mW
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 20-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 20-TSSOP
包装: 托盘
输出数目和类型: 2 电压,单极
采样率(每秒): 192k
配用: 598-1152-ND - BOARD EVAL FOR CS4351 DAC
16
DS566F1
CS4351
4.3
Digital Interface Format
The device will accept audio samples in 1 of 4 digital interface formats in Stand-Alone mode, as illustrated
in Table 6, and 1 of 6 formats in Control Port mode, as illustrated in Table 7.
4.3.1
Stand-Alone Mode
The desired format is selected via the DIF1 and DIF0 pins. For an illustration of the required relationship
between the LRCK, SCLK and SDIN, see Figures 5 through 7. For all formats, SDIN is valid on the rising
edge of SCLK. Also, SCLK must have at least 32 cycles per LRCK period in format 2, and 48 cycles per
LRCK period in format 3.
4.3.2
Control Port Mode
The desired format is selected via the DIF2, DIF1 and DIF0 bits in the Mode Control 2 register (see section
Section 6.2.1). For an illustration of the required relationship between LRCK, SCLK and SDIN, see
Figures 5 through 7. For all formats, SDIN is valid on the rising edge of SCLK. Also, SCLK must have at
Sample Rate
(kHz)
MCLK (MHz)
256x
384x
512x
768x
1024x
1152x
32
8.1920
12.2880
16.3840
24.5760
32.7680
36.8640
44.1
11.2896
16.9344
22.5792
33.8688
45.1584
48
12.2880
18.4320
24.5760
36.8640
49.1520
Table 3. Single-Speed Mode Standard Frequencies
Sample Rate
(kHz)
MCLK (MHz)
128x
192x
256x
384x
512x
64
8.1920
12.2880
16.3840
24.5760
32.7680
88.2
11.2896
16.9344
22.5792
33.8688
45.1584
96
12.2880
18.4320
24.5760
36.8640
49.1520
Table 4. Double-Speed Mode Standard Frequencies
Sample Rate
(kHz)
MCLK (MHz)
64x
96x
128x
192x
256x
176.4
11.2896
16.9344
22.5792
33.8688
45.1584
192
12.2880
18.4320
24.5760
36.8640
49.1520
Table 5. Quad-Speed Mode Standard Frequencies
= Denotes clock modes which are NOT auto detected
DIF0
DIF1
DESCRIPTION
FORMAT
FIGURE
00
I2S, up to 24-bit Data
0
01
Left Justified, up to 24-bit Data
1
10
Right Justified, 24-bit Data
2
11
Right Justified, 16-bit Data
3
Table 6. Digital Interface Format - Stand-Alone Mode
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