参数资料
型号: CS4353-CNZR
厂商: CIRRUS LOGIC INC
元件分类: DAC
中文描述: SERIAL INPUT LOADING, 24-BIT DAC, QCC24
封装: 4 MM, LEAD FREE, QFN-24
文件页数: 9/25页
文件大小: 278K
代理商: CS4353-CNZR
DS803F3
17
CS4353
4.8
Initialization
When power is first applied, the DAC enters a reset (low power) state at the beginning of the initialization
sequence. In this state, the AOUTx pins are weakly pulled to ground and VBIAS is connected to VA.
The device will remain in the reset state until the RESET pin is brought high. Once the RESET pin is high,
the internal digital circuitry is reset and the DAC enters a power-down state until MCLK is applied. Alterna-
tively, if no external reset control is required, the internal power-on reset can be used by tying the RESET
pin to VL (see Section 4.7).
Once MCLK is valid, the device enters an initialization state in which the charge pump powers up and charg-
es the capacitors for both the positive and negative high-voltage supplies.
Once LRCK and SCLK are valid, the number of MCLK cycles is counted relative to the LRCK period to de-
termine the MCLK/LRCK frequency ratio. Next, the device enters the power-up state in which the interpo-
lation and decimation filters and delta-sigma modulators are turned on, the internal voltage reference,
VBIAS, powers up to normal operation, the analog output pull-down resistors are removed, and power is
applied to the output amplifiers.
After this power-up state sequence is complete, normal operation begins and analog output is generated.
If valid MCLK, LRCK, and SCLK are applied to the DAC before RESET is set high, the total time from RE-
SET being set high to the analog audio output from AOUTx is less than 50 ms.
See Figure 9 for a diagram of the device’s states and transition conditions.
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