参数资料
型号: CS5364-DQZ
厂商: Cirrus Logic Inc
文件页数: 15/42页
文件大小: 0K
描述: IC ADC 4CH 114DB 216KHZ 48-LQFP
标准包装: 250
位数: 24
采样率(每秒): 216k
数据接口: 串行
转换器数目: 1
功率耗散(最大): 580mW
电压电源: 模拟和数字
工作温度: -40°C ~ 105°C
安装类型: 表面贴装
封装/外壳: 48-LQFP
供应商设备封装: 48-LQFP(7x7)
包装: 管件
输入数目和类型: 4 个差分,单极
产品目录页面: 755 (CN2011-ZH PDF)
配用: CDB5364-ND - EVALUATION BOARD FOR CS5364
其它名称: 598-1697
22
DS625F4
CS5364
4.5
Serial Audio Interface (SAI) Format
The SAI port consists of two timing pins (SCLK, LRCK/FS) and four audio data output pins (SDOUT1/TDM,
SDOUT2, SDOUT3/TDM and SDOUT4). The CS5364 output is serial data in IS, Left-Justified (LJ), or Time
Division Multiplexed (TDM) digital audio interface formats. These formats are available to the user in both
Stand-Alone Mode and Control Port Mode.
4.5.1
IS and LJ Format
The IS and LJ formats are both two-channel protocols. During one LRCK period, two channels of data are
transmitted, odd channels first, then even. The MSB is always clocked out first.
In Slave Mode, the number of SCLK cycles per channel is fixed as described under “Serial Audio Interface
- IS/LJ Timing” on page 15. In Slave Mode, if more than 32 SCLK cycles per channel are received from a
master controller, the CS5364 will fill the longer frame with trailing zeros. If fewer than 24 SCLK cycles per
channel are received from a master, the CS5364 will truncate the serial data output to the number of SCLK
cycles received. For a complete overview of serial audio interface formats, please refer to Cirrus Logic Ap-
plication Note AN282.
Figure 10. IS Format
Figure 11. LJ Format
Odd Channels 1,3, ...
Even Channels 2,4, ...
LRCK
receiver latches data on rising edges of SCLK
SDOUT
SCLK
MSB
...
LSB
MSB
...
LSB
MSB
Odd Channels 1,3, ...
Even Channels 2,4, ...
LRCK
receiver latches data on rising edges of SCLK
MSB
...
LSB
MSB
...
LSB
SDOUT
SCLK
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