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参数资料
| 型号： | CS5376A-IQZR |
| 厂商： | Cirrus Logic Inc |
| 文件页数： | 2/49页 |
| 文件大小： | 0K |
| 描述： | IC FILTER DGTL MULTI-CH 64-TQFP |
| 标准包装： | 1,000 |
| 滤波器类型： | 数字 |
| 滤波器数： | 4 |
| 滤波器阶数： | 2nd |
| 电源电压： | 3 V ~ 5 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-LQFP |
| 供应商设备封装： | 64-TQFP（10x10） |
| 包装： | 带卷 (TR) |
| 配用： | 598-1778-ND - EVALUATION BOARD FOR CS5376 |
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2008 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FUSB2805 Rev. 1.0.3
10
F
USB2
8
0
5
—
USB2
.0
High
-S
pee
d
OTG
Tra
nsc
e
iv
e
rw
ith
UL
P
I
Inter
fac
e
ULPI Signals
D [7:0]
STP
NXT
DIR
TXCMD
RegWr
SuspendM
Data
Turn
Around
CLOCK
Low Power Mode Signals
tCS
tSTP
1
Note: The second STP pulse indicates the exit of low-power (suspend) mode
Figure 6. Entering Low-Power Mode
Exiting Low-Power Mode
If the FUSB2805 has been in suspend at least 2 s, the
link may signal the FUSB2805 to exit low-power mode
by asynchronously asserting STP. The FUSB2805
immediately starts to wake up its internal circuitry. Upon
meeting the ULPI timing requirements the FUSB2805
then de-asserts DIR, ensuring a minimum of 5 cycles of
CLOCK have been driven before de-asserting DIR and
setting SuspendM=1b (in Function Control Register).
The link de-asserts STP in the cycle following the de-
assertion of DIR. There is one cycle of data bus
turnaround provided after the assertion of DIR, during
which the value of D[7:0] is not valid. Upon completion
of the turnaround cycle the FUSB2805 begins driving
the signals as described in Table 1.
ULPI Signals
D [7:0]
STP
NXT
DIR
SuspendM
Turn
Around
PHY Output CLOCK
Synchronous Mode Signals
Low-Power Mode Signals
tWU
tCWU
tCD
Figure 7. Exiting Low-Power Mode when FUSB2805 Provides Output CLOCK
6-Pin Full-Speed / Low-Speed Serial Mode
This mode of operation is provided for links that contain
legacy FS/LS functionality and enables a cost-effective
upgrade path to HS functionality.
To enter 6-pin serial mode, the link controller sets the
6PIN_FSLS_SERIAL bit in the interface control register
to logic 1. To exit 6-pin serial mode, the link controller
asserts STP.
An INT signal is also provided to inform the link of USB
events. If the link requires CLOCK to be running during 6-
pin serial mode, the CLK_SUSPENDM register bit must
be set to logic 1b before entering 6-pin serial mode.
The FUSB2805 requires CLKIN to be kept running when
in 6-pin mode. In 6-pin serial mode, the data bus
assignments are changed to those described in Table
2. Examples of the signaling of data packets are shown
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相关代理商/技术参数 |
参数描述 |
|---|---|
| CS5376-BQ | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CS5378 | 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:Low-power Single-channel Decimation Filter |
| CS5378_08 | 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:Low-power Single-channel Decimation Filter |
| CS5378-IS | 功能描述:特殊用途放大器 IC LP Single-Ch Decimation Filter RoHS:否 制造商:Texas Instruments 通道数量:Single 共模抑制比（最小值）: 输入补偿电压: 工作电源电压:3 V to 5.5 V 电源电流:5 mA 最大功率耗散: 最大工作温度:+ 70 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:QFN-20 封装:Reel |
| CS5378-ISZ | 功能描述:特殊用途放大器 IC LP Single-Ch Decimation Filter RoHS:否 制造商:Texas Instruments 通道数量:Single 共模抑制比（最小值）: 输入补偿电压: 工作电源电压:3 V to 5.5 V 电源电流:5 mA 最大功率耗散: 最大工作温度:+ 70 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:QFN-20 封装:Reel |
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