参数资料
| 型号： | CS5530-ISZR |
| 厂商： | Cirrus Logic Inc |
| 文件页数： | 4/36页 |
| 文件大小： | 0K |
| 描述： | IC ADC 24BIT 1CH W/LNA 20-SSOP |
| 标准包装： | 1,000 |
| 位数： | 24 |
| 采样率（每秒）： | 3.84k |
| 数据接口： | 串行 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 45mW |
| 电压电源： | 模拟和数字，双 ± |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-SSOP（0.209"，5.30mm 宽） |
| 供应商设备封装： | 20-SSOP |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 1 个差分，单极；1 个差分，双极 |
| 配用： | 598-1158-ND - BOARD EVAL FOR CS5530 |
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CS5530
12
DS742F3
2.1.1 Analog Input Span
The full-scale input signal that the converter can dig-
itize is a function of the reference voltage connected
between the VREF+ and VREF- pins. The full-scale
input span of the converter is
((VREF+) – (VREF-))/(64Y), where 64 is the gain
of the amplifier and Y is 2 for VRS = 0, or Y is 1 for
VRS = 1. VRS is the Voltage Reference Select bit,
and must be set according to the differential voltage
applied to the VREF+ and VREF- pins on the part.
See section 2.3.4 for more details.
With a 2.5 V reference, the full-scale biploar input
range is equal to ±2.5/64, or about ±39 mV. Note
that these input ranges assume the calibration regis-
ters are set to their default values (i.e. Gain = 1.0 and
Offset = 0.0). The gain setting in the Gain Register
can be altered to map the digital codes of the con-
verter to set full scales from 1 mV to 40 mV.
2.1.2 Voltage Noise Density Performance
Figure 5 illustrates the measured voltage noise den-
sity versus frequency from 0.025 Hz to 10 Hz. The
device was powered with ±2.5 V supplies, using
30 Sps OWR, bipolar mode, and with the input
short bit enabled.
2.1.3 No Offset DAC
An offset DAC was not included in the CS5530 be-
cause the high dynamic range of the converter
eliminates the need for one. The offset register can
be manipulated by the user to mimic the function of
a DAC if desired.
2.2 Overview of ADC Register Structure
and Operating Modes
The CS5530 ADC has an on-chip controller, which
includes a number of user-accessible registers. The
registers are used to hold offset and gain calibration
results, configure the chip's operating modes, hold
conversion instructions, and to store conversion
data words. Figure 6 depicts a block diagram of the
on-chip controller’s internal registers.
The converter has 32-bit registers to function as the
offset and the gain calibration registers. These reg-
isters hold calibration results. The contents of these
registers can be read or written by the user. This al-
lows calibration data to be off-loaded into an exter-
nal EEPROM. The user can also manipulate the
contents of these registers to modify the offset or
the gain slope of the converter.
The converter includes a 32-bit configuration reg-
ister which is used for setting options such as the
power down modes, resetting the converter, short-
ing the analog input, enabling logic outputs, and
other user options.
The following pages document how to initialize the
converter and perform offset and gain calibrations.
Each of the bits of the configuration register is de-
scribed. Also the Command Register Quick Refer-
ence can be used to decode all valid commands (the
first 8-bits into the serial port).
2.2.1 System Initialization
The CS5530 provide no power-on-reset function.
To initialize the ADC, the user must perform a soft-
ware reset via the configuration register. Before
accessing the configuration register, the user must
insure serial port synchronization by using the Se-
rial Port Initialization sequence. This sequence re-
sets the serial port to the command mode and is
accomplished by transmitting at least 15 SYNC1
command bytes (0xFF hexadecimal), followed by
one SYNC0 command (0xFE hexadecimal). Note
that this sequence can be initiated at anytime to
reinitialize the serial port. To complete the system
1
10
100
1000
0.025
0.10
1.00
10.00
Frequency (Hz)
Figure 5. Measured Voltage Noise Density, 64x
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相关代理商/技术参数 |
参数描述 |
|---|---|
| CS5531 | 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:16 BIT AND 24 BIT ADCS WITH ULTRA LOW NOISE PGIA |
| CS5531_08 | 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:16-bit and 24-bit ADCs with Ultra-low-noise PGIA |
| CS5531-AS | 功能描述:模数转换器 - ADC 2-Ch 16-Bit ADCs w/ Ultra Low Noise PGIA RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| CS5531-ASR | 功能描述:模数转换器 - ADC IC 16-Bit ADCs w/UltraLw Noise PGIA RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| CS5531-ASZ | 功能描述:模数转换器 - ADC 2-Ch 16-Bit ADCs w/ Ultra Low Noise PGIA RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
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