参数资料
型号: CS7620-IQ
厂商: CIRRUS LOGIC INC
元件分类: 消费家电
英文描述: CCD IMAGER ANALOG PROCESSOR
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP64
封装: 10 X 10 X 1.40 MM, MS-026, TQFP-64
文件页数: 48/70页
文件大小: 1032K
代理商: CS7620-IQ
CS7620
48
DS301PP2
4.30
Horizontal Timing Control - H1
Default = 68h; Read/Write (address 29h)
Bit Number
Bit Name
Default
7
6
5
4
3
2
1
0
Reserved
-
h1d
1
h1f_reg2
1
h1f_reg1
0
h1f_reg0
1
h1f_reg2
0
h1f_reg1
0
h1f_reg0
0
Bit
Mnemonic
Function
7
-
Reserved
H1 Default Setting:
During the vertical shift time, the horizontal clocks are
held in one state. This bit controls whether H1 is held high or low during this
time.
6
h1d
A “0” indicates that the signal state is low, a “1” indicates that the signal state
is high.
H1 Falling Edge:
The phase of the falling edge of H1 can be programmed
through this register. The falling edge of H1 corresponds to the rising edge of
the internally selected clock. The phases of these clocks are shown in Figure
19, with the complemented clocks being the inverse of these.
5
h1f_reg2
0 = t0
1 = t1
2 = t2
3 = t3
4 = t4
5 = t5
6 = t6
7 = t7
(See Figure 19)
H1 Rising Edge:
The phase of the rising edge of H1 can be programmed
through this register. The rising edge of H1 corresponds to the rising edge of
the internally selected clock. The phases of these clocks are shown in Figure
19, with the complemented clocks being the inverse of these.
4
h1f_reg1
3
h1f_reg0
2
h1f_reg2
0 = t0
1 = t1
2 = t2
3 = t3
4 = t4
5 = t5
6 = t6
7 = t7
(See Figure 19)
1
h1f_reg1
0
h1f_reg0
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