参数资料
型号: CS7620-IQ
厂商: CIRRUS LOGIC INC
元件分类: 消费家电
英文描述: CCD IMAGER ANALOG PROCESSOR
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP64
封装: 10 X 10 X 1.40 MM, MS-026, TQFP-64
文件页数: 62/70页
文件大小: 1032K
代理商: CS7620-IQ
CS7620
62
DS301PP2
4.53
DAC #1 Control
Default = 00h; Read/Write (address 40h)
4.54
DAC #2 Control
Default = 00h; Read/Write (address 41h)
4
3
2
1
0
clk_divide4
clk_divide3
clk_divide2
clk_divide1
clk_divide0
Clock Divider:
The master clock frequency can be an integer multiple of the
pixel clock rate. This register contains the number by which to divide the mas-
ter clock frequency in order to get the pixel clock frequency. If a ‘0’ is pro-
grammed here, the divider is bypassed and the master clock is assumed to be
at the pixel rate.
Bit Number
Bit Name
Default
7
6
5
4
3
2
1
0
dac_cntl17
0
dac_cntl16
0
dac_cntl15
0
dac_cntl14
0
dac_cntl13
0
dac_cntl12
0
dac_cntl11
0
dac_cntl10
0
Bit
7
6
5
4
3
2
1
0
Mnemonic
dac_cntl17
dac_cntl16
dac_cntl15
dac_cntl14
dac_cntl13
dac_cntl12
dac_cntl11
dac_cntl10
Function
DAC#1 Control:
This is the digital input code to the general purpose DAC#1
which will then be converted into the analog current output. Each LSB in this
word will increment the output by ~8.7 μA in low current mode and ~34 μA in
high current mode.
Bit Number
Bit Name
Default
7
6
5
4
3
2
1
0
dac_cntl27
0
dac_cntl26
0
dac_cntl25
0
dac_cntl24
0
dac_cntl23
0
dac_cntl22
0
dac_cntl21
0
dac_cntl20
0
Bit
7
6
5
4
3
2
1
0
Mnemonic
dac_cntl27
dac_cntl26
dac_cntl25
dac_cntl24
dac_cntl23
dac_cntl22
dac_cntl21
dac_cntl20
Function
DAC #2 Control:
This is the digital input code to the general purpose DAC#2
which will then be converted into the analog current output. Each LSB in this
word will increment the output by ~8.7 μA in low current mode and ~34 μA in
high current mode.
Bit
Mnemonic
Function
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