参数资料
| 型号： | CS8420-DSZ |
| 厂商： | Cirrus Logic Inc |
| 文件页数： | 49/94页 |
| 文件大小： | 0K |
| 描述： | IC CONV S/R DGTL AUDIO 28-SOIC |
| 标准包装： | 27 |
| 类型： | 采样率转换器 |
| 应用： | 数字音频 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 28-SOIC |
| 包装： | 管件 |
| 产品目录页面： | 759 (CN2011-ZH PDF) |
| 其它名称： | 598-1729 |
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DS245F4
53
CS8420
EMPH - Pre-Emphasis Indicator Output
EMPH is low when the incoming AES3 data indicates the presence of 50/15
μs pre-emphasis. When the AES3 data
indicates the absence of pre-emphasis or the presence of other than 50/15
μs pre-emphasis EMPH is high. This is
also a start-up option pin, and requires a 47 k
Ω resistor to either VD+ or DGND, which determines the AD2 address
bit for the control port in IC mode.
Audio Output Interface:
SDOUT - Serial Audio Output Port Data Output
Audio data serial output pin.
OSCLK - Serial Audio Output Port Bit Clock Input or Output
Serial bit clock for audio data on the SDOUT pin.
OLRCK - Serial Audio Output Port Left/Right Clock Input or Output
Word rate clock for the audio data on the SDOUT pin. The frequency will be at the output sample rate (Fso)
AES3/SPDIF Transmitter Interface:
TCBL - Transmit Channel Status Block Start
This pin can be configured as an input or output. When operated as output, TCBL is high during the first sub-frame
of a transmitted channel status block, and low at all other times. When operated as input, driving TCBL high for at
least three OMCK (or RMCK, depending on which clock is operating the AES3 encoder block) clocks will cause the
next transmitted sub-frame to be the start of a channel status block.
TXN, TXP - Differential Line Driver Outputs
Differential line driver outputs, transmitting AES3 type data. Drivers are pulled to low while the CS8420 is in the reset
state.
Control Port Signals:
SCL/CCLK - Control Port Clock
SCL/CCLK is the serial control interface clock, and is used to clock control data bits into and out of the CS8420.
AD0/CS - Address Bit 0 (IC) / Control Port Chip Select (SPI)
A falling edge on this pin puts the CS8420 into SPI Control Port mode. With no falling edge, the CS8420 defaults to
IC mode. In IC mode, AD0 is a chip address pin. In SPI mode, CS is used to enable the control port interface on
the CS8420.
AD1/CDIN - Address Bit 1 (IC) / Serial Control Data In (SPI)
In IC mode, AD1 is a chip address pin. In SPI mode, CDIN is the input data line for the control port interface
SDA/CDOUT - Serial Control Data I/O (IC) / Data Out (SPI)
In IC mode, SDA is the control I/O data line. SDA is open drain and requires an external pull-up resistor to VD+. In
SPI mode, CDOUT is the output data from the control port interface on the CS8420.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| CS8420-DSZR | 功能描述:音频 DSP IC Digital Audio Sample Rate Convertr RoHS:否 制造商:Texas Instruments 工作电源电压: 电源电流: 工作温度范围: 安装风格: 封装 / 箱体: 封装:Tube |
| CS8421 | 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:32-bit, 192-kHz Asynchronous Sample Rate Converter |
| CS8421_06 | 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:32-bit, 192 kHz Asynchronous Sample Rate Converter |
| CS8421_09 | 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:32-bit, 192 kHz Asynchronous Sample Rate Converter |
| CS8421_10 | 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:32-bit, 192-kHz Asynchronous Sample Rate Converter |
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