参数资料
型号: CS8420-DSZ
厂商: Cirrus Logic Inc
文件页数: 75/94页
文件大小: 0K
描述: IC CONV S/R DGTL AUDIO 28-SOIC
标准包装: 27
类型: 采样率转换器
应用: 数字音频
安装类型: 表面贴装
封装/外壳: 28-SOIC(0.295",7.50mm 宽)
供应商设备封装: 28-SOIC
包装: 管件
产品目录页面: 759 (CN2011-ZH PDF)
其它名称: 598-1729
DS245F4
77
CS8420
ILRCK - Serial Audio Input Port Left/Right Clock
Input or Output Word rate clock for the audio data on the SDIN pin.
APMS - Serial Audio Input Port Master or Slave.
APMS should be connected to VD+ to set serial audio input port as a master, or connected to DGND to set the port
as a slave.
AES3/SPDIF Transmitter Interface:
TXN, TXP - Differential Line Driver Outputs
Differential line driver outputs, transmitting AES3 type data. Drivers are pulled to low while the CS8420 is in the reset
state.
TCBL - Transmit Channel Status Block Start
When operated as output, TCBL is high during the first sub-frame of a transmitted channel status block, and low at
all other times. When operated as input, driving TCBL high for at least three OMCK clocks will cause the current
transmitted sub-frame to be the start of a channel status block.
TCBLD - Transmit Channel Status Block Direction Input
Connect TCBLD to VD+ to set TCBL as an output. Connect TCBLD to DGND to set TCBL as an input.
EMPH - Pre-Emphasis Indicator Input
In mode 6B, EMPH pin low sets the 3 EMPH channel status bits to indicate 50/15
μs pre-emphasis. If EMPH is high
the 3 EMPH channel status bits are set to 000 indicating no pre-emphasis.
COPY/C - COPY Channel Status Bit Input or C Bit Input
In mode 6B, the COPY/C pin determines the state of the COPY, PRO and L Channel Status bits in the outgoing
AES3 type data stream (See Table 15). In mode 6A, the COPY/C pin becomes the direct C bit input data pin.
ORIG - ORIG Channel Status Bit Input
In mode 6B, the ORIG pin determines the state of the COPY, PRO and L Channel Status bits in the outgoing AES3
type data stream. See Table 15.
AUDIO - Audio Channel Status Bit Input
In mode 6B, the AUDIO pin determines the state of the audio/non audio Channel Status bit in the outgoing AES3
type data stream.
V - Validity Bit Input
In modes 6A and 6B, the V pin input determines the state of the validity bit in the outgoing AES3 transmitted data.
This pin is sampled on both edges of the ILRCK.
U - User Data Bit Input
In modes 6A and 6B, the U pin input determines the state of the user data bit in the outgoing AES3 transmitted data.
This pin is sampled on both edges of the ILRCK.
CEN - C Bit Input Enable Mode Input
The CEN pin determines how the channel status data bits are input. When CEN is low, Hardware mode 6A is se-
lected, where the COPY/C, ORIG, EMPH and AUDIO pins are used to enter selected channel status data. When
CEN is high, Hardware mode 6B is selected, where the COPY/C pin is used to enter serial channel status data.
相关PDF资料
PDF描述
CS8421-CNZ IC SAMPLE RATE CONVERTER 20QFN
CS8427-DZZ IC TXRX DGTL AUDIO 96KHZ 28TSSOP
CY28329ZXC IC CLOCK CK408B PLUMAS 56SSOP
CY28346OXC IC CLOCK DIFF OUT CK408 56SSOP
CY28346ZI-2 IC CLOCK DIFF OUT CK408 56TSSOP
相关代理商/技术参数
参数描述
CS8420-DSZR 功能描述:音频 DSP IC Digital Audio Sample Rate Convertr RoHS:否 制造商:Texas Instruments 工作电源电压: 电源电流: 工作温度范围: 安装风格: 封装 / 箱体: 封装:Tube
CS8421 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:32-bit, 192-kHz Asynchronous Sample Rate Converter
CS8421_06 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:32-bit, 192 kHz Asynchronous Sample Rate Converter
CS8421_09 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:32-bit, 192 kHz Asynchronous Sample Rate Converter
CS8421_10 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:32-bit, 192-kHz Asynchronous Sample Rate Converter