参数资料
| 型号： | CS8420-DSZ |
| 厂商： | Cirrus Logic Inc |
| 文件页数： | 59/94页 |
| 文件大小： | 0K |
| 描述： | IC CONV S/R DGTL AUDIO 28-SOIC |
| 标准包装： | 27 |
| 类型： | 采样率转换器 |
| 应用： | 数字音频 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 28-SOIC |
| 包装： | 管件 |
| 产品目录页面： | 759 (CN2011-ZH PDF) |
| 其它名称： | 598-1729 |
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DS245F4
CS8420
RMCK - Input Section Recovered Master Clock Output
Input section recovered master clock output. Will be at a frequency of 256x the input sample rate (Fsi).
LOCK - PLL Lock Indicator Output
LOCK low indicates that the PLL is locked. This is also a start-up option pin, and requires a pull-up or pull-down
resistor.
Audio Output Interface:
SDOUT - Serial Audio Output Port Data Output
Audio data serial output pin. This is also a start-up option pin, and requires a pull-up or pull-down resistor.
OSCLK - Serial Audio Output Port Bit Clock Input or Output
Serial bit clock for audio data on the SDOUT pin.
OLRCK - Serial Audio Output Port Left/Right Clock Input or Output
Word rate clock for the audio data on the SDOUT pin. The frequency will be at the output sample rate (Fso).
AES3/SPDIF Transmitter Interface:
TXN, TXP - Differential Line Driver Outputs
Differential line driver outputs, transmitting AES3 type data. Drivers are pulled to low while the CS8420 is in the reset
state.
TCBL - Transmit Channel Status Block Start
When operated as output, TCBL is high during the first sub-frame of a transmitted channel status block, and low at
all other times. When operated as input, driving TCBL high for at least three OMCK clocks will cause the current
transmitted sub-frame to be the start of a channel status block.
CUVEN - C, U and V bit Input Enable Mode Input
The CUVEN pin determines how the channel status data, user data and validity bit is input. When CUVEN is low,
Hardware mode 2A is selected, where the EMPH/V, COPY/C and ORIG/U pins are used to enter selected channel
status data. When CUVEN is high, hardware 2B is selected, where the EMPH/V, COPY/C and ORIG/U pins are
used to enter serial C, U and V data.
EMPH/V - Pre-Emphasis Indicator Input or V Bit Input
In mode 2A, EMPH/V low sets the 3 EMPH channel status bits to indicate 50/15
μs pre-emphasis. EMPH/V high
sets the 3 EMPH bits to 000 indicating no pre-emphasis. In mode 2B, EMPH/V low sets the V bit to indicate valid
audio. EMPH/V high sets the V-bit to indicate non-valid audio.
COPY/C - COPY Channel Status Bit Input or C Bit Input
In mode 2A, the COPY/C pin determines the state of the COPY, PRO and L Channel Status bits in the outgoing
AES3 type data stream (See Table 9). In mode 2B, COPY/C becomes the direct C bit input data pin.
ORIG/U - ORIG Channel Status Bit Input or U Bit Input
In mode 2A, the ORIG/U pin determines the state of the COPY, PRO and L Channel Status bits in the outgoing AES3
type data stream. (See Table 9). In mode 2B, ORIG/U becomes the direct U bit input data pin.
相关PDF资料 |
PDF描述 |
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| CS8421-CNZ | IC SAMPLE RATE CONVERTER 20QFN |
| CS8427-DZZ | IC TXRX DGTL AUDIO 96KHZ 28TSSOP |
| CY28329ZXC | IC CLOCK CK408B PLUMAS 56SSOP |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| CS8420-DSZR | 功能描述:音频 DSP IC Digital Audio Sample Rate Convertr RoHS:否 制造商:Texas Instruments 工作电源电压: 电源电流: 工作温度范围: 安装风格: 封装 / 箱体: 封装:Tube |
| CS8421 | 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:32-bit, 192-kHz Asynchronous Sample Rate Converter |
| CS8421_06 | 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:32-bit, 192 kHz Asynchronous Sample Rate Converter |
| CS8421_09 | 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:32-bit, 192 kHz Asynchronous Sample Rate Converter |
| CS8421_10 | 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:32-bit, 192-kHz Asynchronous Sample Rate Converter |
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