参数资料
| 型号： | CS8420-DSZ |
| 厂商： | Cirrus Logic Inc |
| 文件页数： | 80/94页 |
| 文件大小： | 0K |
| 描述： | IC CONV S/R DGTL AUDIO 28-SOIC |
| 标准包装： | 27 |
| 类型： | 采样率转换器 |
| 应用： | 数字音频 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 28-SOIC |
| 包装： | 管件 |
| 产品目录页面： | 759 (CN2011-ZH PDF) |
| 其它名称： | 598-1729 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页当前第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页
DS245F4
81
CS8420
15. CHANNEL STATUS AND USER DATA BUFFER MANAGEMENT
The CS8420 has a comprehensive channel status (C) and user (U) data buffering scheme, which allows automatic
management of channel status blocks and user data. Alternatively, sufficient control and access is provided to allow
the user to completely manage the C and U data via the control port.
15.1
AES3 Channel Status(C) Bit Management
The CS8420 contains sufficient RAM to store a full block of C data for both A and B channels (192x2 = 384
bits), and also 384 bits of U information. The user may read from or write to these RAMs via the control port.
Unlike the audio data, it is not possible to 'sample-rate' convert the C bits. This is because specific meanings
are associated with fixed-length data patterns, which should not be altered. Since the output data rate of the
CS8420 will differ from the input rate when sample-rate conversion is done, it is not feasible to directly trans-
fer incoming C data to the output. The CS8420 manages the flow of channel status data at the block level,
meaning that entire blocks of channel status information are buffered at the input, synchronized to the output
timebase, and then transmitted. The buffering scheme involves a cascade of three block-sized buffers,
named D,E, and F as shown in Figure 37. The MSB of each byte represents the first bit in the serial C data
stream. For example, the MSB of byte 0 (which is at control port address 20h) is the consumer/professional
bit for channel status block A.
The first buffer, D, accepts incoming C data from the AES receiver. The 2nd buffer, E, accepts entire blocks
of data from the D buffer. The E buffer is also accessible from the control port, allowing read and writing of
the C data. The 3rd buffer (F) is used as the source of C data for the AES3 transmitter. The F buffer accepts
block transfers from the E buffer.
If the input rate is slower than the output rate (so that in a given time interval, more channel status blocks
are transmitted than received), some buffered C blocks will be transmitted multiple times. If the input rate is
faster than the output rate, some will not be transmitted at all. This is illustrated in (Figure 38). In this manner,
channel status block integrity is maintained. If the transmitted sample count bits are important in the appli-
cation, then they will need to be updated via the control port by the microcontroller for every outgoing block.
Control Port
From
AES3
Receiver
To
AES3
Transmitter
E
24
words
8-bits
AB
DF
Received
Data
Buffer
Transmit
Data
Buffer
Figure 37. Channel Status Data Buffer Structure
相关PDF资料 |
PDF描述 |
|---|---|
| CS8421-CNZ | IC SAMPLE RATE CONVERTER 20QFN |
| CS8427-DZZ | IC TXRX DGTL AUDIO 96KHZ 28TSSOP |
| CY28329ZXC | IC CLOCK CK408B PLUMAS 56SSOP |
| CY28346OXC | IC CLOCK DIFF OUT CK408 56SSOP |
| CY28346ZI-2 | IC CLOCK DIFF OUT CK408 56TSSOP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| CS8420-DSZR | 功能描述:音频 DSP IC Digital Audio Sample Rate Convertr RoHS:否 制造商:Texas Instruments 工作电源电压: 电源电流: 工作温度范围: 安装风格: 封装 / 箱体: 封装:Tube |
| CS8421 | 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:32-bit, 192-kHz Asynchronous Sample Rate Converter |
| CS8421_06 | 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:32-bit, 192 kHz Asynchronous Sample Rate Converter |
| CS8421_09 | 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:32-bit, 192 kHz Asynchronous Sample Rate Converter |
| CS8421_10 | 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:32-bit, 192-kHz Asynchronous Sample Rate Converter |
发布紧急采购，3分钟左右您将得到回复。