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参数资料
| 型号： | CY28317PVXC-2T |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 15/20页 |
| 文件大小： | 0K |
| 描述： | IC CLK FTG VIA PL/E133T 48SSOP |
| 标准包装： | 1,000 |
| 类型： | 时钟/频率发生器 |
| PLL： | 是 |
| 输入： | 晶体 |
| 输出： | HCSL，LVCMOS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:20 |
| 差分 - 输入:输出： | 无/是 |
| 频率 - 最大： | 248MHz |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-BSSOP（0.295"，7.50mm 宽） |
| 供应商设备封装： | 48-SSOP |
| 包装： | 带卷 (TR) |
CY28317-2
....................... Document #: 38-07094 Rev. *B Page 4 of 20
Serial Data Interface
The CY28317-2 features a two-pin, serial data interface that
can be used to configure internal register settings that control
particular device functions.
Data Protocol
The clock driver serial protocol supports byte/word Write,
byte/word Read, block Write and block Read operations from
the controller. For block Write/Read operations, the bytes must
be accessed in sequential order from lowest to highest byte
with the ability to stop after any complete byte has been trans-
ferred. For byte/word Write and byte Read operations, the
system controller can access individual indexed bytes. The
offset of the indexed byte is encoded in the command code.
The definition for the command code is defined as shown in
Table 2. Command Code Definition
Bit
Descriptions
7
0 = Block read or block write operation
1 = Byte/Word read or byte/word write operation
6:0
Byte offset for byte/word read or write operation. For block read or write operations, these bits
need to be set at ‘0000000’.
Table 3. Block Read and Block Write Protocol
Block Write Protocol
Block Read Protocol
Bit
Description
Bit
Description
1Start
2:8
Slave address – 7 bits
2:8
Slave address – 7 bits
9Write
10
Acknowledge from slave
10
Acknowledge from slave
11:18
Command Code – 8 bits
‘00000000’ stands for block operation
11:18
Command Code – 8 bits
‘00000000’ stands for block operation
19
Acknowledge from slave
19
Acknowledge from slave
20:27
Byte count – 8 bits
20
Repeat start
28
Acknowledge from slave
21:27
Slave address – 7 bits
29:36
Data byte 0 – 8 bits
28
Read
37
Acknowledge from slave
29
Acknowledge from slave
38:45
Data byte 1 – 8 bits
30:37
Byte count from slave – 8 bits
46
Acknowledge from slave
38
Acknowledge
...
Data byte N/Slave acknowledge...
39:46
Data byte from slave – 8 bits
...
Data byte N – 8 bits
47
Acknowledge
...
Acknowledge from slave
48:55
Data byte from slave – 8 bits
...
Stop
56
Acknowledge
...
Data bytes from slave/Acknowledge
...
Data byte N from slave - 8 bits
...
Not acknowledge
...
Stop
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相关代理商/技术参数 |
参数描述 |
|---|---|
| CY28317ZC-2 | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:FTG for Mobile VIA PL133T and PLE133T Chipsets |
| CY28317ZC-2T | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:FTG for Mobile VIA PL133T and PLE133T Chipsets |
| CY28322 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Clocks and Buffers |
| CY28322-2 | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:133-MHz Spread Spectrum Clock Synthesizer with Differential CPU Outputs |
| CY28322ZC-2 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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