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参数资料
| 型号： | CY28446LFXCT |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 14/19页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK CALISTOGA CK410M 64QFN |
| 标准包装： | 2,000 |
| 类型： | 时钟/频率发生器 |
| PLL： | 是 |
| 主要目的： | Intel CPU 服务器 |
| 输入： | LVTTL，晶体 |
| 输出： | HCSL，LVCMOS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 3:20 |
| 差分 - 输入:输出： | 无/是 |
| 频率 - 最大： | 200MHz |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-VFQFN 裸露焊盘 |
| 供应商设备封装： | 64-QFN（9x9） |
| 包装： | 带卷 (TR) |
CY28446
.......................Document #: 001-00168 Rev *F Page 4 of 19
Frequency Select Pins (FS_A, FS_B, and FS_C)
Apply the appropriate logic levels to FSA, FSB, and FSC
before CK-PWRGD assertion to achieve host clock frequency
selection. When the clock chip sampled HIGH on CK-PWRGD
and indicates that VTT voltage is stable then FSA, FSB, and
FSC input values are sampled. This process employs a
one-shot functionality and once the CK-PWRGD sampled a
valid HIGH, all other FSA, FSB, FSC and CK-PWRGD transi-
tions are ignored except in test mode
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers are individually enabled or disabled. The
registers associated with the Serial Data Interface initialize to
their default setting at power-up, making this interface
optional. Clock device register changes are made at system
initialization if required. The interface cannot be used during
system operation for power management functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, access the bytes in sequential
order from lowest to highest byte (most significant bit first) with
the ability to stop after complete byte has been transferred. For
byte write and byte read operations, the system controller
accesses individually indexed bytes. The offset of the indexed
byte is encoded in the command code, as described in
The block write and block read protocol is outlined in Table 4
while Table 5 outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h).
Table 3. Command Code Definition
Bit
Description
7
0 = Block read or block write operation, 1 = Byte read or byte write operation.
(6:0)
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be
'0000000'.
Table 4. Block Read and Block Write Protocol
Block Write Protocol
Block Read Protocol
Bit
Description
Bit
Description
1Start
1
Start
8:2
Slave address–7 bits
8:2
Slave address–7 bits
9
Write
9
Write
10
Acknowledge from slave
10
Acknowledge from slave
18:11
Command Code–8 bits
18:11
Command Code–8 bits
19
Acknowledge from slave
19
Acknowledge from slave
27:20
Byte Count–8 bits
(Skip this step if I2C_EN bit set)
20
Repeat start
28
Acknowledge from slave
27:21
Slave address–7 bits
36:29
Data byte 1–8 bits
28
Read = 1
37
Acknowledge from slave
29
Acknowledge from slave
45:38
Data byte 2–8 bits
37:30
Byte Count from slave–8 bits
46
Acknowledge from slave
38
Acknowledge
....
Data Byte/Slave Acknowledges
46:39
Data byte 1 from slave–8 bits
....
Data Byte N–8 bits
47
Acknowledge
....
Acknowledge from slave
55:48
Data byte 2 from slave–8 bits
....
Stop
56
Acknowledge
....
Data bytes from slave/Acknowledge
....
Data Byte N from slave–8 bits
....
NOT Acknowledge
....
Stop
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