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参数资料
| 型号： | CY28446LFXCT |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 18/19页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK CALISTOGA CK410M 64QFN |
| 标准包装： | 2,000 |
| 类型： | 时钟/频率发生器 |
| PLL： | 是 |
| 主要目的： | Intel CPU 服务器 |
| 输入： | LVTTL，晶体 |
| 输出： | HCSL，LVCMOS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 3:20 |
| 差分 - 输入:输出： | 无/是 |
| 频率 - 最大： | 200MHz |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-VFQFN 裸露焊盘 |
| 供应商设备封装： | 64-QFN（9x9） |
| 包装： | 带卷 (TR) |
CY28446
.......................Document #: 001-00168 Rev *F Page 8 of 19
.
The CY28446 requires a Parallel Resonance Crystal. Substi-
tuting a series resonance crystal causes the CY28446 to
operate at the wrong frequency and violate the ppm specifi-
cation. For most applications there is a 300-ppm frequency
shift between series and parallel crystals due to incorrect
loading
Crystal Loading
Crystal loading plays a critical role in achieving low ppm perfor-
mance. To realize low ppm performance, use the total capac-
itance the crystal sees to calculate the appropriate capacitive
loading (CL).
Figure 1 shows a typical crystal configuration using the two
trim capacitors. It is important that the trim capacitors are in
series with the crystal. It is not true that load capacitors are in
parallel with the crystal and are approximately equal to the
load capacitance of the crystal.
.
Calculating Load Capacitors
In addition to the standard external trim capacitors, consider
the trace capacitance and pin capacitance to calculate the
crystal loading correctly. Again, the capacitance on each side
Byte 8: Control Register 7
Bit
@Pup
Name
Description
7
0
Reserved
Reserved set to 0
6
1
SRC[T/C]10
SRC[T/C]10 Output Enable
0 = Disable (Tri-state), 1 = Enable
5
1
SRC[T/C]9
SRC[T/C]9 Output Enable
0 = Disable (Tri-state), 1 = Enable
4
1
SRC[T/C]8
SRC[T/C]8 Output Enable
0 = Disable (Tri-state), 1 = Enable
3
0
Reserved
Reserved set to 0
2
0
SRC10
Allow control of SRC[T/C]10 with assertion of OEA#
0 = Free running, 1 = Stopped with OEA#
1
0
SRC9
Allow control of SRC[T/C]9 with assertion of OEB#
0 = Free running, 1 = Stopped with OEB#
0
SRC8
Allow control of SRC[T/C]8 with assertion of OEA#
0 = Free running, 1 = Stopped with OEA#
Byte 9: Control Register 8
Bit
@Pup
Name
Description
7
0
PCI3
33-MHz Output drive strength
0 = Low, 1 = High
6
0
PCI2
33-MHz Output drive strength
0 = Low, 1 = High
5
0
PCI1
33-MHz Output drive strength
0 = Low, 1 = High
4
0
PCI0
33-MHz Output drive strength
0 = Low, 1 = High
3
0
PCIF0
33-MHz Output drive strength
0 = Low, 1 = High
2
1
Reserved
Reserved set to 1
1
Reserved
Reserved set to 1
0
1
Reserved
Reserved set to 1
Crystal Recommendations
Frequency
(Fund)
Cut
Loading
Load Cap
Drive
(max.)
Shunt Cap
(max.)
Motional
(max.)
Tolerance
(max.)
Stability
(max.)
Aging
(max.)
14.31818 MHz
AT
Parallel
20 pF
0.1 mW
5 pF
0.016 pF
35 ppm
30 ppm
5 ppm
Figure 1. Crystal Capacitive Clarification
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