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参数资料
| 型号： | CY28446LFXCT |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 17/19页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK CALISTOGA CK410M 64QFN |
| 标准包装： | 2,000 |
| 类型： | 时钟/频率发生器 |
| PLL： | 是 |
| 主要目的： | Intel CPU 服务器 |
| 输入： | LVTTL，晶体 |
| 输出： | HCSL，LVCMOS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 3:20 |
| 差分 - 输入:输出： | 无/是 |
| 频率 - 最大： | 200MHz |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-VFQFN 裸露焊盘 |
| 供应商设备封装： | 64-QFN（9x9） |
| 包装： | 带卷 (TR) |
CY28446
.......................Document #: 001-00168 Rev *F Page 7 of 19
Byte 5: Control Register 5
Bit
@Pup
Name
Description
7
0
Reserved
Reserved set to 0
6
0
CPU[T/C]2
CPU[T/C]2 Stop Drive Mode
0 = Driven when CPU_STP# asserted, 1 = Tri-state when CPU_STP#
asserted
5
0
CPU[T/C]1
CPU[T/C]1 Stop Drive Mode
0 = Driven when CPU_STP# asserted, 1 = Tri-state when CPU_STP#
asserted
4
0
CPU[T/C]0
CPU[T/C]0 Stop Drive Mode
0 = Driven when CPU_STP# asserted, 1 = Tri-state when CPU_STP#
asserted
3
0
SRC[T/C]
SRC[T/C] PWRDWN Drive Mode
0 = Driven when PD asserted, 1 = Tri-state when PD asserted
2
0
CPU[T/C]2
CPU[T/C]2 PWRDWN Drive Mode
0 = Driven when PD asserted, 1 = Tri-state when PD asserted
1
0
CPU[T/C]1
CPU[T/C]1 PWRDWN Drive Mode
0 = Driven when PD asserted, 1 = Tri-state when PD asserted
0
CPU[T/C]0
CPU[T/C]0 PWRDWN Drive Mode
0 = Driven when PD asserted, 1 = Tri-state when PD asserted
Byte 6: Control Register 6
Bit
@Pup
Name
Description
7
0
REF/N or Tri-state Select REF/N or Tri-state Select
1 = REF/N, 0 = Tri-state
6
0
Test Mode
Test Mode Control
1 = Ref/N or Tristate, 0 = Normal Operation
5
1
Reserved
Reserved set to 1
4
0
REF
REF Output Drive Strength
0 = Low, 1 = High
3
1
PCI and PCIF clock
outputs except those set
to free running
SW PCI_STP Function
0 = SW PCI_STP assert, 1 = SW PCI_STP deassert
When this bit is set to 0, all STOPPABLE PCI and PCIF outputs are
stopped in a synchronous manner with no short pulses.
When this bit is set to 1, all STOPPED PCI and PCIF outputs resumes in
a synchronous manner with no short pulses.
2
HW
FS_C
FSC Reflects the value of the FS_C pin sampled on power-up
0 = FSC was low during VTT_PWRGD# assertion
1
HW
FS_B
FSB Reflects the value of the FS_B pin sampled on power-up
0 = FSB was low during VTT_PWRGD# assertion
0
HW
FS_A
FSA Reflects the value of the FS_A pin sampled on power-up
0 = FSA was low during VTT_PWRGD# assertion
Byte 7: Vendor ID
Bit
@Pup
Name
Description
7
0
Revision Code Bit 3
6
0
Revision Code Bit 2
5
1
Revision Code Bit 1
4
1
Revision Code Bit 0
3
1
Vendor ID Bit 3
2
0
Vendor ID Bit 2
1
0
Vendor ID Bit 1
0
Vendor ID Bit 0
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