参数资料
型号: CY7C1371BV25-83BGC
厂商: CYPRESS SEMICONDUCTOR CORP
元件分类: SRAM
英文描述: 512K X 36 ZBT SRAM, 10 ns, PBGA119
封装: 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
文件页数: 11/25页
文件大小: 709K
代理商: CY7C1371BV25-83BGC
CY7C1373BV25
CY7C1371BV25
Document #: 38-05250 Rev. *A
Page 19 of 25
Switching Waveforms (continued)
ADV/LD
CLK
ADDRESS
CE
1a
Data
In/Out
tCYC
tCH tCL
tALS
tALH
RA1
tAH
tAS
tCES tCEH
tCDV
Q1
= DON’T CARE
= UNDEFINED
The combination of WE and BWSx(x = a, b, c, d) define a write cycle (see Write Cycle Description table).
Out
B
e
gi
n
R
e
ad
Bu
rs
tRe
a
d
tCLZ
tDOH
CE is the combination of CE1, CE2, and CE3. All chip enables need to be active in order to select
the device. Any chip enable can deselect the device. RAx stands for Read Address X, WA stands for
Device
originally deselected
Write Address X, Dx stands for Data-in for location X, Qx stands for Data-out for location X. CEN held
WA2
Q1+1
Out
Q1+2
Out
Q1+3
Out
RA3
tCLZ
tCHZ
D2+1
In
D2+2
In
D2+3
In
D2
In
tCDV
Q3
Out
tDS
tDH
Bu
rs
tRe
a
d
Bu
rs
tRe
a
d
Be
g
in
W
ri
te
Bu
rs
tWr
it
e
Bu
rs
tW
ri
te
Bu
rs
tW
ri
te
B
e
gi
n
R
ead
B
u
rst
R
ead
Bu
rs
tRe
a
d
Burst Sequences
BWSx
tWES
tWEH
WE
tWS tWH
LOW. During burst writes, byte writes can be conducted by asserting the appropriate BWSx input signals.
Burst order determined by the state of the MODE input. CEN held LOW. OE held LOW.
Out
Q3+1
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