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参数资料
| 型号： | CY7C341B-25RI |
| 厂商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分类： | PLD |
| 英文描述： | UV PLD, 40 ns, CPGA84 |
| 封装： | WINDOWED, PGA-84 |
| 文件页数： | 1/12页 |
| 文件大小： | 339K |
| 代理商： | CY7C341B-25RI |
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192-Macrocell MAX EPLD
CY7C341B
Cypress Semiconductor Corporation
3901 North First Street
San Jose
, CA 95134
408-943-2600
Document #: 38-03016 Rev. *C
Revised April 22, 2004
Features
192 macrocells in 12 logic array blocks (LABs)
Eight dedicated inputs, 64 bidirectional I/O pins
Advanced 0.65-micron CMOS technology to increase
performance
Programmable interconnect array
384 expander product terms
Available in 84-pin HLCC, PLCC, and PGA packages
Functional Description
The CY7C341B is an Erasable Programmable Logic Device
(EPLD) in which CMOS EPROM cells are used to configure
logic functions within the device. The MAX architecture is
100% user-configurable, allowing the devices to accom-
modate a variety of independent logic functions.
The 192 macrocells in the CY7C341B are divided into 12 Logic
Array Blocks (LABs), 16 per LAB. There are 384 expander
product terms, 32 per LAB, to be used and shared by the
macrocells within each LAB. Each LAB is interconnected with
a programmable interconnect array, allowing all signals to be
routed throughout the chip.
The speed and density of the CY7C341B allows it to be used
in a wide range of applications, from replacement of large
amounts of 7400-series TTL logic, to complex controllers and
multifunction chips. With greater than 37 times the functionality
of 20-pin PLDs, the CY7C341B allows the replacement of over
75 TTL devices. By replacing large amounts of logic, the
CY7C341B reduces board space, part count, and increases
system reliability.
Each LAB contains 16 macrocells. In LABs A, F, G, and L, 8
macrocells are connected to I/O pins and eight are buried,
while for LABs B, C, D, E, H, I, J, and K, four macrocells are
connected to I/O pins and 12 are buried. Moreover, in addition
to the I/O and buried macrocells, there are 32 single product
term logic expanders in each LAB. Their use greatly enhances
the capability of the macrocells without increasing the number
of product terms in each macrocell.
Selection Guide
7C341B-25
7C341B-35
Unit
Maximum Access Time
25
35
ns
相关PDF资料 |
PDF描述 |
|---|---|
| CY7C341B-35RC | UV PLD, 55 ns, CPGA84 |
| CY7C341B-35RI | UV PLD, 55 ns, CPGA84 |
| CY7C341B-25HC | UV PLD, 40 ns, CQCC84 |
| CY7C341B-25HI | UV PLD, 40 ns, CQCC84 |
| CY7C341B-35HC | UV PLD, 55 ns, CQCC84 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| CY7C341B-35JI | 制造商:Cypress Semiconductor 功能描述:CPLD MAX 制造商:QP Semiconductor 功能描述:7C341B CYP DIE 35NS-PLCC |
| CY7C341B-35RI | 制造商:Cypress Semiconductor 功能描述:CPLD MAX? Family 3.75K Gates 192 Macro Cells 33.3MHz 0.65um Technology 5V 84-Pin Windowed PGA |
| CY7C342-25HC | 制造商:Cypress Semiconductor 功能描述:CMOS EPLD SMD 7C342 PLCC68 5V |
| CY7C342-30HC | 制造商:Cypress Semiconductor 功能描述: 制造商:Cypress Semiconductor 功能描述:Complex Erasable Programmable Logic Device, 128 Cell, 30ns, 68 Pin, Ceramic, PLCC |
| CY7C34235HMB | 制造商:CYPRESS 功能描述:New |
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