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APPLICATION INFORMATION
CURRENT CONSUMPTION
OUTPUT VOLTAGE STABILITY
DRIVING RESISTIVE AND CAPACITIVE
SETTLING TIME AND OUTPUT GLITCH
CROSSTALK AND AC PERFORMANCE
DIFFERENTIAL AND INTEGRAL
SLAS431B – JUNE 2005 – REVISED OCTOBER 2006
In addition, the DAC8554 can achieve typical ac
performance of 96dB signal-to-noise ratio (SNR) and
85dB total harmonic distortion (THD), making the
The DAC8554 typically consumes a maximum of
DAC8554 a solid choice for applications requiring
208
A at AV
DD = 5V and 180A at AVDD = 3V for
high SNR at output frequencies at or below 10kHz.
each active channel, including reference current
consumption. Additional current consumption can
occur at the digital inputs if VIH << IOVDD. For most
efficient power operation, CMOS logic levels are
The DAC8554 exhibits excellent temperature stability
recommended at the digital inputs to the DAC.
of 5ppm/
°C typical output voltage drift over the
In power-down mode, typical current consumption is
specified temperature range of the device. This
175nA per channel. A delay time of 10ms to 20ms
stability enables the output voltage of each channel
after a power-down command is issued to the DAC
to stay within a
±25V window for a ±1°C ambient
is typically sufficient for the power-down current to
temperature change.
drop below 10
A.
Good
power-supply
rejection
ratio
(PSRR)
performance reduces supply noise present on AVDD
from appearing at the outputs to well below 10
V-s.
LOADS
Combined with good dc noise performance and true
16-bit differential linearity, the DAC8554 becomes a
The DAC8554 output stage is capable of driving
perfect choice for closed-loop control applications.
loads of up to 1000pF while remaining stable. Within
the offset and gain error margins, the DAC8554 can
operate rail-to-rail when driving a capacitive load.
Resistive loads of 2k
can be driven by the
PERFORMANCE
DAC8554 while achieving good load regulation.
The DAC8554 settles to
±0.003% of its full-scale
When the outputs of the DAC are driven to the
range within 10
s, driving a 200pF 2k load. For
positive rail under resistive loading, the PMOS
good settling performance, the outputs should not
transistor of each Class-AB output stage can enter
approach the top and bottom rails. Small signal
into the linear region. When this scenario occurs, the
settling time is under 1
s, enabling data update rates
added IR voltage drop deteriorates the linearity
exceeding 1MSPS for small code changes.
performance of the DAC. This deterioration only
occurs within approximately the top 100mV of the
Many
applications
are
sensitive
to
undesired
DAC output voltage characteristic. Under resistive
transient signals such as glitch. The DAC8554 has a
loading conditions, good linearity is preserved as
proprietary, ultra-low glitch architecture addressing
long as the output voltage is at least 100mV below
such
applications.
Code-to-code
glitches
rarely
the AVDD voltage.
exceed 1mV and they last under 0.3
s. Typical glitch
energy is an outstanding 0.15nV-s. Theoretical
worst-case glitch should occur during a 256LSB step,
but it is so low, it cannot be detected.
The DAC8554 architecture uses separate resistor
strings for each DAC channel in order to achieve
ultra-low crosstalk performance. dc crosstalk seen at
NONLINEARITY
one channel during a full-scale change on the
neighboring channel is typically less than 0.5LSBs.
The DAC8554 uses precision thin film resistors to
The ac crosstalk measured (for a full-scale, 1kHz
achieve monotonicity and good linearity. Typical
sine wave output generated at one channel, and
linearity error is
±4LSBs, with a ±0.3mV error for a
measured at the remaining output channel) is
5V range. Differential linearity is typically
±0.25LSBs,
typically under –100dB.
with a
±19V error for a consecutive code change.
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