参数资料
型号: DAC8554IPWR
厂商: TEXAS INSTRUMENTS INC
元件分类: DAC
英文描述: SERIAL INPUT LOADING, 12 us SETTLING TIME, 16-BIT DAC, PDSO16
封装: GREEN, PLASTIC, TSSOP-16
文件页数: 6/31页
文件大小: 1039K
代理商: DAC8554IPWR
www.ti.com
THEORY OF OPERATION
DAC SECTION
DAC
Register
REF(+)
ResistorString
REF( )
-
V
L
REF
V
H
REF
V
OUT
62kW
50kW
V
OUTX + 2
V
REFL
) (VREFH * VREFL)
D
IN
65536
RESISTOR STRING
V
REFH
V
REFL
R
V
REF
2
R
DIVIDER
ToOutputAmplifier
(2xGain)
OUTPUT AMPLIFIER
SERIAL INTERFACE
SLAS431B – JUNE 2005 – REVISED OCTOBER 2006
The architecture of each channel of the DAC8554
consists of a resistor-string DAC followed by an
output buffer amplifier. Figure 45 shows a simplified
block diagram of the DAC architecture.
Figure 45. DAC8554 Architecture
The input coding for each device is unipolar straight
binary, so the ideal output voltage is given by:
where DIN = decimal equivalent of the binary code
that is loaded to the DAC register; it can range from
0 to 65535.
The resistor string section is shown in Figure 46. It is
simply a divide-by-2 resistor followed by a string of
Figure 46. Resistor String
resistors. The code loaded into the DAC register
determines at which node on the string the voltage is
tapped off. This voltage is then applied to the output
The write sequence begins by bringing the SYNC
amplifier by closing one of the switches connecting
line LOW. Data from the DIN line are clocked into the
the string to the amplifier.
24-bit shift register on each falling edge of SCLK.
The serial clock frequency can be as high as 50MHz,
making the DAC8554 compatible with high-speed
DSPs. On the 24th falling edge of the serial clock,
Each output buffer amplifier is capable of generating
the last data bit is clocked into the shift register and
rail-to-rail voltages on its output that approaches an
the shift register gets locked. Further clocking does
output range of 0V to AVDD (gain and offset errors
not change the shift register data. Once 24 bits are
must be taken into account). Each buffer is capable
locked into the shift register, the eight MSBs are
of driving a load of 2k
in parallel with 1000pF to
used as control bits and the 16 LSBs are used as
GND. The source and sink capabilities of the output
data. After receiving the 24th falling clock edge, The
amplifier can be seen in the Typical Characteristics.
DAC8554 decodes the eight control bits and 16 data
bits to perform the required function, without waiting
for a SYNC rising edge. A new SPI sequence starts
The DAC8554 uses a 3-wire serial interface (SYNC,
at the next falling edge of SYNC. A rising edge of
SCLK, and DIN), which is compatible with SPI,
SYNC before the 24-bit sequence is complete resets
QSPI, and Microwire interface standards, as well
the SPI interface; no data transfer occurs.
as most DSPs. See the Serial Write Operation timing
diagram for an example of a typical write sequence.
14
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DAC8554IPW SERIAL INPUT LOADING, 12 us SETTLING TIME, 16-BIT DAC, PDSO16
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