参数资料
型号: DAC8554IPWR
厂商: TEXAS INSTRUMENTS INC
元件分类: DAC
英文描述: SERIAL INPUT LOADING, 12 us SETTLING TIME, 16-BIT DAC, PDSO16
封装: GREEN, PLASTIC, TSSOP-16
文件页数: 18/31页
文件大小: 1039K
代理商: DAC8554IPWR
www.ti.com
LAYOUT
SLAS431B – JUNE 2005 – REVISED OCTOBER 2006
As with the GND connection, AVDD should be
connected to a positive power-supply plane or trace
A precision analog component requires careful
that is separate from the connection for digital logic
layout,
adequate
bypassing,
and
clean,
until they are connected at the power-entry point. In
well-regulated power supplies.
addition, a 1
F to 10F capacitor in parallel with a
0.1
F bypass capacitor is strongly recommended. In
The DAC8554 offers single-supply operation, and it
some
situations,
additional
bypassing
may
be
will often be used in close proximity with digital logic,
required, such as a 100
F electrolytic capacitor or
microcontrollers, microprocessors, and digital signal
even
a
Pi
filter
made
up
of
inductors
and
processors. The more digital logic present in the
capacitors—all designed to essentially low-pass filter
design and the higher the switching speed, the more
the supply, removing the high-frequency noise.
difficult it is to keep digital noise from appearing at
the output.
Up to four DAC8554 devices can be used on a single
SPI bus without any glue logic to create a high
Due to the single ground pin of the DAC8554, all
channel count solution. Special attention is required
return currents, including digital and analog return
to avoid digital signal integrity problems when using
currents for the DAC, must flow through a single
multiple DAC8554s on the same SPI bus. Signal
point. Ideally, GND would be connected directly to an
integrity of SYNC, SCLK, and DIN lines will not be an
analog ground plane. This plane would be separate
issue as long as the rise times of these digital signals
from
the
ground
connection
for
the
digital
are longer than six times the propagation delay
components until they
were
connected
at
the
between any two DAC8554 devices. Propagation
power-entry point of the system.
speed is approximately six inches/ns on standard
The power applied to AVDD should be well-regulated
printed circuit boards (PCBs). Therefore, if the digital
and low-noise. Switching power supplies and dc/dc
signal rise time is 1ns, the distance between any two
converters often have high-frequency glitches or
DAC8554s has to be further apart on the PCB, and
spikes riding on the output voltage. In addition, digital
the signal rise times should be reduced by placing
components
can
create
similar
high-frequency
series resistors at the drivers for SYNC, SCLK, and
spikes. This noise can easily couple into the DAC
DIN lines. If the largest distance between any two
output voltage through various paths between the
DAC8554s must be six inches, the rise time should
power connections and analog output.
be reduced to 6ns with an RC network formed by the
series resistor at the digital driver and the total trace
and input capacitance on the PCB.
25
相关PDF资料
PDF描述
DAC8554IPW SERIAL INPUT LOADING, 12 us SETTLING TIME, 16-BIT DAC, PDSO16
DAC8564IAPWR SERIAL INPUT LOADING, 12 us SETTLING TIME, 16-BIT DAC, PDSO16
DAC8564IBPW SERIAL INPUT LOADING, 12 us SETTLING TIME, 16-BIT DAC, PDSO16
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