参数资料
型号: DAC8554IPWR
厂商: TEXAS INSTRUMENTS INC
元件分类: DAC
英文描述: SERIAL INPUT LOADING, 12 us SETTLING TIME, 16-BIT DAC, PDSO16
封装: GREEN, PLASTIC, TSSOP-16
文件页数: 9/31页
文件大小: 1039K
代理商: DAC8554IPWR
www.ti.com
SYNC INTERRUPT
POWER-ON RESET
24thFallingEdge
SCLK
SYNC
D
IN
1
DB22
DB0
DB1 DB0
InvalidWrite-SyncInterrupt:
SYNC HIGHBefore24thFallingEdge
ValidWrite-Buffer/DACUpdate:
SYNC HIGHAfter24thFallingEdge
2
1
2
DB23
DB22
DB23
SLAS431B – JUNE 2005 – REVISED OCTOBER 2006
In a normal write sequence, the SYNC line is kept
The DAC8554 contains a power-on reset circuit that
LOW for at least 24 falling edges of SCLK and the
controls the output voltage during power-up. On
addressed DAC register is updated on the 24th
power-up, the DAC registers are filled with zeros and
falling edge. However, if SYNC is brought HIGH
the output voltages are set to zero-scale; they
before the 24th falling edge, it acts as an interrupt to
remain that way until a valid write sequence and load
the write sequence; the shift register is reset and the
command are made to the respective DAC channel.
write sequence is discarded. Neither an update of
The power-on reset is useful in applications where it
the data buffer contents, DAC register contents, nor
is important to know the state of the output of each
a change in the operating mode occurs (see
DAC while the device is in the process of powering
up. No device pin should be brought high before
power is applied to the device.
Figure 48. Interrupt and Valid SYNC Timing
17
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