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参数资料
| 型号： | DC1029A |
| 厂商： | Linear Technology |
| 文件页数： | 10/32页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD FOR LTC2928 |
| 设计资源： | DC1029A Design File DC1029A Schematic |
| 标准包装： | 1 |
| 主要目的： | 电源管理，电源监控器/跟踪器/序列发生器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | LTC2928 |
| 主要属性： | 4 通道电源定序器 |
| 已供物品： | 板 |
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LTC2928
PIN FUNCTIONS
OVA: Over Voltage Adjust Input. After configuring the un-
dervoltage thresholds, bias this input to set the overvoltage
threshold for all positive supplies. Leave the pin floating
to set an overvoltage threshold approximately 32% above
the undervoltage threshold. Tie OVA to V CC to move the
overvoltage threshold above 1V. Consult the Applications
Information for details on OVA biasing.
PTMR: Power Good Timer. Attach an external capacitor to
ground to set the maximum time allowed for all supplies
to reach their configured undervoltage threshold during
sequence-up phase (or all supplies below their sequence-
down threshold during sequence-down phase). The timer
is started when the first enable (EN) is raised (or lowered).
The power good timing scale factor is 4000ms/ μ F. A 0.1 μ F
capacitor generates a 400ms delay time. If any supply is
late, a sequence fault is generated. FLT pulls low and all
supply enable outputs are pulled low. Disable the power
good timer by grounding PTMR. Consult Applications
Information for more details.
RDIS: Reset Disable Three State Input. Typically used for
supply margining applications. Pull RDIS high or low to
force RST high. Leave the RDIS input open to allow RST
to operate normally.
REF: Reference Output. REF is used to offset negative
supplies connected through resistance to V1. The refer-
ence will move during sequence-up and sequence-down
operation to effect the selected thresholds. The buffered
reference sources 1mA and sinks up to 200 μ A of current.
The reference drives a bypass capacitor of up to 1000pF
without oscillation.
RST : Reset Output. If any supply is below its undervolt-
age threshold, RST pulls low. RST pulls high after all
supplies are above their undervoltage threshold for the
configured delay time (configure delay time using the
RTMR pin). The RST output has a weak pull-up to V CC
and may be pulled above V CC using an external pull-up.
RST is guaranteed low with V CC down to 0.5V. Configure
the RST to FLT relationship using the MS1, MS2 inputs.
See Applications Information for details. Leave the RST
output open if unused.
RTMR: Reset Timer. Attach an external capacitor to
ground to set a reset delay time of 4000ms/ μ F. Floating
RTMR generates a minimum delay of approximately 50 μ s.
10
A 0.047 μ F capacitor will generate a 190ms delay time.
RT1-RT4: Resistive Time Position Configuration Inputs.
Place a single resistor from V CC to each input to select one
of eight time positions in which to turn-on or turn-off each
enable output (see Application Information for RT table).
Each RT input numerically corresponds to a respective
EN output and monitor input. During sequencing-up, an
enable output (EN) pulls high at the start of its chosen time
position. During sequencing-down, an enable output (EN)
pulls low at the start of its chosen time position (sequence-
down position is the reverse of sequence-up). To remove
a monitor channel from participation, command any en-
able off by pulling its corresponding RT input to ground.
Prior to sequencing, any enable may be commanded on
by pulling its corresponding RT input to V CC . Maximum
capacitive load is 150pF.
SQT1, SQT2: Sequencing Threshold Three State Configura-
tion Inputs. Select sequencing thresholds as a percentage
of the 0.5V supply monitor threshold for positive supplies
and as a percentage of REF for negative supplies. For
sequencing-up choose from 33%, 67% or 100%. For
sequencing-down choose from 100%, 67%, 33% or 10%.
See Applications Information for configuration table.
STMR: Sequence Timer. Attach an external capacitor to
ground to set the adjacent time-position delay between
sequenced supplies. For supplies in adjacent time posi-
tions, this delay resides between the previous supply
crossing its sequence-up (down) threshold and the next
enable (EN) pulling high (low). For a supply in time po-
sition 1, the sequence delay is the time from ON going
high to its enable pulling high. The sequence timing scale
factor is 8670ms/ μ F. Floating STMR generates a minimum
sequencing time delay of approximately 100 μ s. A 3300pF
capacitor will generate a 29ms delay time. Referring to the
timing diagrams, the sequence delay time is equivalent
to the cascade (CAS) pin high time. Consult Applications
Information for details.
V CC : Power Supply Input/Output. All internal circuits
are powered from V CC . Bypass V CC with at least 0.1 μ F
to ground in close proximity to this pin (1 μ F minimum
when using HV CC ).
VSEL: Voltage Monitor Select Input. Tie to ground to
select four positive inputs. Tie to V CC for three positive
2928f
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