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参数资料
| 型号： | DC1029A |
| 厂商： | Linear Technology |
| 文件页数： | 25/32页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD FOR LTC2928 |
| 设计资源： | DC1029A Design File DC1029A Schematic |
| 标准包装： | 1 |
| 主要目的： | 电源管理，电源监控器/跟踪器/序列发生器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | LTC2928 |
| 主要属性： | 4 通道电源定序器 |
| 已供物品： | 板 |
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LTC2928
APPLICATIO S I FOR ATIO
RnB UV TH ( V )
= – 1
C PTMR =
= 0 . 1 μ F
C RTMR ( F ) =
g.Undervoltagethresholds
The positive supply monitor undervoltage threshold at all
of the monitor inputs is 0.5V. Connect a resistive divider
from the sensed voltage to ground. Connect the tap point
to the respective high impedance monitor input. Specify
the required undervoltage threshold (UV TH ) and calculate
the divider ratio using
RnA 0 . 5 V
This application requires –6.5% undervoltage thresholds
for all supplies. For the 1.8V supply monitored on V3,
the undervoltage threshold is 1.683V (1.8V x 0.935). The
necessary divider ratio is
400ms
4 . 0 M ?
i. Reset delay time
The reset delay time is the additional time that RST is held
low after all monitor inputs are above their undervoltage
threshold. It is also the additional time that OV is held low
(after an overvoltage event) after all monitor inputs are
below their overvoltage threshold. When the reset timer
expires, RST and/or OV is allowed to pull high. The reset
delay time (t RTMR ) is set with a capacitor from the RTMR
pin to ground. Calculate the reset capacitance from
t RTMR (s)
4 . 0 M ?
R 3 B
R 3 A
=
1 . 683
0 . 5 V
– 1 ≈ 2 . 37
For this application, the reset delay time is 190ms,
yielding
=
– 1 ≈ 3 . 68
=
– 1 ≈ 1 . 81
=
– 1 ≈ 5 . 17
C RTMR ( F ) =
= 0 . 047 μ F
C PTMR ( F ) =
V OVA ( V ) =
? OV TH ( V )
V OVA ( V ) =
? 2 . 25 = 0 . 667 V
AgoodchoiceforR3Bis23.7kandR3Ais10k.Allsequence
thresholds are a percentage of the configured undervoltage
threshold. The remaining ratios are:
R 1 B 2 . 338
R 1 A 0 . 5 V
R 2 B 1 . 403
R 2 A 0 . 5 V
R 4 B 3 . 086
R 4 A 0 . 5 V
h. Power-good timing
The “power-good” time defines the maximum time allowed
for all monitored voltages to reach their undervoltage
threshold when sequencing-up, or the sequence-down
threshold (when sequencing-down) with respect to the time
of the first enabled (disabled) supply. If the “power-good”
timer expires, a sequence fault occurs. The “power-good”
time (t PTMR ) is set with a capacitor from the PTMR pin to
ground. Calculate the “power-good” capacitance from
t PTMR (s)
4 . 0 M ?
For this application, the “power-good” time is 400ms,
yielding
190ms
4 . 0 M ?
j. Overvoltage thresholds
Configure the OVA pin to set the global overvoltage
thresholds. The application requires overvoltage thresholds
at approximately 25% above the nominal supply voltage.
For the 1.8V supply, the overvoltage threshold (OV TH )
equals 2.25V (1.8V x 1.25). Compute the required value
for V OVA from:
RnA
RnA + RnB
For this application,
10 k
10 k + 23 . 7 k
From the curves in Figures 16 and 17, the approximate
value for V OVA is achieved by leaving the OVA pin open.
Since the other monitor inputs were configured for the
same relative undervoltage level, the relative overvoltage
levels for the other supplies are the same (+ 25%).
The application requires a fast shutdown upon overvoltage.
To generate a fault upon an overvoltage condition, tie OV to
FLT . The fault condition shuts down all controlled supplies.
2928f
25
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