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参数资料
| 型号： | DC1029A |
| 厂商： | Linear Technology |
| 文件页数： | 13/32页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD FOR LTC2928 |
| 设计资源： | DC1029A Design File DC1029A Schematic |
| 标准包装： | 1 |
| 主要目的： | 电源管理，电源监控器/跟踪器/序列发生器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | LTC2928 |
| 主要属性： | 4 通道电源定序器 |
| 已供物品： | 板 |
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LTC2928
OPERATIO
At the beginning of the sequence-up phase, a current
source begins to charge the STMR capacitance. When the
sequence timer has expired the CAS pin pulls low. At this
time, any enable (EN) scheduled (using the RT inputs) for
“time position 1” pulls high, allowing a supply (or supplies)
to be turned on. The CAS pin is held low until all monitored
inputs in the current time position exceed their selected
sequencing-up threshold (25 μ s minimum).
Once all supply monitor inputs cross their sequencing-up
threshold, or if no enable was selected for the current time
position, the CAS pin is allowed to pull high. The STMR
capacitor begins to charge again, moving the system to
“time position 2”. This process repeats until the system
is clocked through “time position 8”.
During the sequence-up phase, supply monitor inputs are
expected to cross their sequence-up threshold (which may
be different from their undervoltage threshold). Any supply
monitor input failing to cross its sequence-up threshold
will stall the process and a sequence-up fault is generated
(if the power-good timer is active). The power-good timer
starts with the first enable output to go high and is cleared
when the last supply monitor input reaches its undervolt-
age threshold. Any supply monitor input failing to cross
its sequence-up threshold before the power-good timer
expires also generates a sequence-up fault. A sequence-
up fault pulls FLT and all supply enable outputs (EN) low.
Use a single capacitor from PTMR to ground to select the
power good time. To disable the power good timer, simply
tie PTMR to ground.
Each comparator switches to its undervoltage threshold
when the respective supply monitor input crosses its
sequence-up threshold. The comparator outputs are
allowed to pull high after the LTC2928 clocks through
time position 8.
After a system fault, fault information is latched to the
CMP outputs. Read the CMP outputs to obtain the fault
type (internally generated sequence-fault, reset-fault, com-
mand-fault or an externally generated fault) and the fault
channel (if any). For more details refer to the discussion
on system faults later in this document.
After the system has clocked through “time position 8”,
the last LTC2928 (defined by a 2.4k to 5.1k pull-up resistor
on DONE ) pulls down on DONE .
Supply Monitor Phase
Once all supply monitor inputs have crossed their
sequence-up thresholds, the LTC2928 enters its supply
monitor phase. As referred to earlier, the comparators
switch to their highly accurate undervoltage thresholds
after crossing their sequence-up threshold. The monitor
thresholds maintain 1.5% accuracy over temperature.
RST pulls high after all supply monitor inputs (V1 to V4)
have been above their undervoltage threshold for the
selected reset delay time. The reset delay is set with a
capacitor attached between RTMR and ground.
The supply monitor comparators will filter out minor
glitches coupled to their inputs. If any supply falls below
threshold with sufficient magnitude and duration, the RST
line pulls low. The reset timer starts once all inputs return
above threshold.
The LTC2928 can be configured to issue a fault if RST
pulls low due to an undervoltage event (see master/slave
configuration table in Applications Information). Upon a
RST fault, FLT and the enable outputs pull low. Use the
fault report capability to determine which input was below
threshold. For more details refer to the discussion on
system faults later in this document.
The reset disable input (RDIS) may be pulled high or low
to force RST high regardless of voltage monitor level. This
feature is useful during voltage margining tests.
Sequence-Down Phase
The sequence-down phase is initiated by pulling the ON
input below 0.97V. This action pulls RST low immediately.
The comparator thresholds (and REF for negative supplies)
are moved to their selected sequence-down thresholds.
Beginning with any supplies in “time position 8”, the en-
able outputs are sequenced-down by pulling enable low
in the reverse order of sequence-up (last on, first off).
During the sequence-down phase, supply monitor
inputs are expected to cross their sequence-down
thresold (which may be different from their undervoltage
threshold) within the selected power good time. Any
supply monitor input failing to cross its sequence-down
threshold will stall the process and a sequence-down fault is
generated (if the power-good timer is active).The power-
2928f
13
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