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参数资料
| 型号： | DC1339A |
| 厂商： | Linear Technology |
| 文件页数： | 13/20页 |
| 文件大小： | 0K |
| 描述： | BOARD SAR ADC LTC2302 |
| 软件下载： | QuikEval System |
| 设计资源： | DC1339A Design File DC1339A Schematic |
| 标准包装： | 1 |
| 系列： | QuikEval™ |
| ADC 的数量： | 1 |
| 位数： | 12 |
| 采样率（每秒）： | 500k |
| 数据接口： | MICROWIRE?，串行，SPI? |
| 输入范围： | ±VREF/2 |
| 在以下条件下的电源（标准）： | 14mW @ 500kSPS |
| 已用 IC / 零件： | LTC2302 |
| 已供物品： | 板 |
| 相关产品： | LTC2302IDD#TRPBF-ND - IC ADC 12-BIT 1CH 500KSPS 10DFN LTC2302IDD#PBF-ND - IC ADC 12BIT 1CH 500KSPS 10-DFN LTC2302CDD#TRPBF-ND - IC ADC 12-BIT 1CH 500KSPS 10DFN LTC2302CDD#PBF-ND - IC ADC 12BIT 1CH 500KSPS 10-DFN |
LTC2302/LTC2306
20
23026fa
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
LINEAR TECHNOLOGY CORPORATION 2008
LT 0908 REV A PRINTED IN USA
TYPICAL APPLICATION
Clock Squaring/Level Shifting Circuit Allows Testing with RF Sine Generator,
Convert Re-Timing Flip-Flop Preserves Low Jitter Clock Timing
SDI
SDO
SCK
CONVST
SERIAL
PORT
ANALOG
INPUT
MUX
CH0 (IN+)
CH1 (IN–)
VREF
CONVERT ENABLE
MASTER
CLOCK
RF SIGNAL
GENERATOR
OR OTHER LOW
JITTER SOURCE
VCC
0.1μF
NC7SVU04P5X
LTC2302
LTC2306
VDD
OVDD
GND
MASTER
CLOCK
CONVERT
ENABLE
JITTER
0.1μF
12-BIT
500ksps
ADC
+
–
10μF
0.1μF
1k
10μF
0.1μF
QD
PRE
VCC
NL17SZ74
CONTROL
LOGIC
(FPGA, CPLD,
DSP, ETC.)
Q CLR
1k
23026 TA02
50Ω
CONVST
DATA TRANSFER
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PART NUMBER
DESCRIPTION
COMMENTS
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LTC1864/LTC1865
16-Bit, 1-/2-Channel 250ksps ADCs in MSOP
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