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参数资料
| 型号： | DC1339A |
| 厂商： | Linear Technology |
| 文件页数： | 16/20页 |
| 文件大小： | 0K |
| 描述： | BOARD SAR ADC LTC2302 |
| 软件下载： | QuikEval System |
| 设计资源： | DC1339A Design File DC1339A Schematic |
| 标准包装： | 1 |
| 系列： | QuikEval™ |
| ADC 的数量： | 1 |
| 位数： | 12 |
| 采样率（每秒）： | 500k |
| 数据接口： | MICROWIRE?，串行，SPI? |
| 输入范围： | ±VREF/2 |
| 在以下条件下的电源（标准）： | 14mW @ 500kSPS |
| 已用 IC / 零件： | LTC2302 |
| 已供物品： | 板 |
| 相关产品： | LTC2302IDD#TRPBF-ND - IC ADC 12-BIT 1CH 500KSPS 10DFN LTC2302IDD#PBF-ND - IC ADC 12BIT 1CH 500KSPS 10-DFN LTC2302CDD#TRPBF-ND - IC ADC 12-BIT 1CH 500KSPS 10DFN LTC2302CDD#PBF-ND - IC ADC 12BIT 1CH 500KSPS 10-DFN |
LTC2302/LTC2306
5
23026fa
TIMING CHARACTERISTICS The l denotes the specications which apply over the full operating temperature
range, otherwise specications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
fSMPL(MAX)
Maximum Sampling Frequency
l
500
kHz
fSCK
Shift Clock Frequency
l
40
MHz
tWHCONV
CONVST High Time
(Note 9)
l
20
ns
tHD
Hold Time SDI After SCK↑
l
2.5
ns
tSUDI
Setup Time SDI Stable Before SCK↑
l
0ns
tWHCLK
SCK High Time
fSCK = fSCK(MAX)
l
10
ns
tWLCLK
SCK Low Time
fSCK = fSCK(MAX)
l
10
ns
tWLCONVST
CONVST Low Time During Data Transfer
(Note 9)
l
410
ns
tHCONVST
Hold Time CONVST Low After Last SCK↓
(Note 9)
l
20
ns
tCONV
Conversion Time
l
1.3
1.6
μs
tACQ
Acquisition Time
7th SCK↑ to CONVST↑ (Note 9)
l
240
ns
tdDO
SDO Data Valid After SCK↓
CL = 25pF (Note 9)
l
10.8
12.5
ns
thDO
SDO Hold Time SCK↓
CL = 25pF
l
4ns
ten
SDO Valid After CONVST↓
CL = 25pF
l
11
15
ns
tdis
Bus Relinquish Time
CL = 25pF
l
11
15
ns
tr
SDO Rise Time
CL = 25pF
4
ns
tf
SDO Fall Time
CL = 25pF
4
ns
tCYC
Total Cycle Time
2μs
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground with VDD and OVDD
wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below ground or above VDD,
they will be clamped by internal diodes. These products can handle input
currents greater than 100mA below ground or above VDD without latchup.
Note 4: VDD = 5V, OVDD = 5V, VREF = 4.096V, fSMPL = 500ksps, unless
otherwise specied.
Note 5: Linearity, offset and full-scale specications apply for a single-
ended analog input with respect to GND for the LTC2306 and IN+ with
respect to IN– tied to GND for the LTC2302.
Note 6: Integral nonlinearity is dened as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: Bipolar zero error is the offset voltage measured from –0.5LSB
when the output code ickers between 0000 0000 0000 and 1111 1111
1111. Unipolar zero error is the offset voltage measured from +0.5LSB
when the output code ickers between 0000 0000 0000 and 0000 0000
0001.
Note 8: Full-scale bipolar error is the worst-case of –FS or +FS untrimmed
deviation from ideal rst and last code transitions and includes the effect
of offset error. Unipolar full-scale error is the deviation of the last code
transition from ideal and includes the effect of offset error.
Note 9: Guaranteed by design, not subject to test.
Note 10: All specications in dB are referred to a full-scale ±2.048V input
with a 4.096V reference voltage.
Note 11: Full linear bandwidth is dened as the full-scale input frequency
at which the SINAD degrades to 60dB or 10 bits of accuracy.
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