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参数资料
| 型号： | DC1339A |
| 厂商： | Linear Technology |
| 文件页数： | 8/20页 |
| 文件大小： | 0K |
| 描述： | BOARD SAR ADC LTC2302 |
| 软件下载： | QuikEval System |
| 设计资源： | DC1339A Design File DC1339A Schematic |
| 标准包装： | 1 |
| 系列： | QuikEval™ |
| ADC 的数量： | 1 |
| 位数： | 12 |
| 采样率（每秒）： | 500k |
| 数据接口： | MICROWIRE?，串行，SPI? |
| 输入范围： | ±VREF/2 |
| 在以下条件下的电源（标准）： | 14mW @ 500kSPS |
| 已用 IC / 零件： | LTC2302 |
| 已供物品： | 板 |
| 相关产品： | LTC2302IDD#TRPBF-ND - IC ADC 12-BIT 1CH 500KSPS 10DFN LTC2302IDD#PBF-ND - IC ADC 12BIT 1CH 500KSPS 10-DFN LTC2302CDD#TRPBF-ND - IC ADC 12-BIT 1CH 500KSPS 10DFN LTC2302CDD#PBF-ND - IC ADC 12BIT 1CH 500KSPS 10-DFN |
LTC2302/LTC2306
16
23026fa
APPLICATIONS INFORMATION
Internal Conversion Clock
The internal conversion clock is factory trimmed to
achieve a typical conversion time (tCONV) of 1.3μs and a
maximum conversion time of 1.6μs over the full operating
temperature range. With a minimum acquisition time of
240ns, a throughput sampling rate of 500ksps is tested
and guaranteed.
Digital Interface
The LTC2302/LTC2306 communicate via a standard
4-wire SPI compatible digital interface. The rising edge
of CONVST initiates a conversion. After the conversion
is nished, pull CONVST low to enable the serial output
(SDO). The ADC then shifts out the digital data in 2’s
complement format when operating in bipolar mode or
in straight binary format when in unipolar mode, based
on the setting of the UNI bit.
For best performance, ensure that CONVST returns low
within 40ns after the conversion starts (i.e., before the rst
bit decision) or after the conversion ends. If CONVST is
low when the conversion ends, the MSB bit will appear at
SDO at the end of the conversion and the ADC will remain
powered up.
Timing and Control
The start of a conversion is triggered by the rising edge
of CONVST. Once initiated, a new conversion cannot be
restarted until the current conversion is complete. Figures 6
and 7 show the timing diagrams for two different examples
of CONVST pulses. Example 1 (Figure 6) shows CONVST
staying HIGH after the conversion ends. If CONVST is high
after the tCONV period, the LTC2302/LTC2306 enter sleep
mode (see Sleep Mode for more details).
When CONVST returns low, the ADC wakes up and the
most signicant bit (MSB) of the output data sequence at
SDO becomes valid after the serial data bus is enabled. All
other data bits from SDO transition on the falling edge of
each SCK pulse. Conguration data (DIN) is loaded into the
LTC2302/LTC2306 at SDI, starting with the rst SCK rising
edge after CONVST returns low. The S/D bit is loaded on
the rst SCK rising edge.
Example 2 (Figure 7) shows CONVST returning low be-
fore the conversion ends. In this mode, the ADC and all
internal circuitry remain powered up. When the conver-
sion is complete, the MSB of the output data sequence
at SDO becomes valid after the data bus is enabled. At
this point(tCONV 1.3μs after the rising edge of CONVST),
pulsing SCK will shift data out at SDO and load congura-
tion data (DIN) into the LTC2302/LTC2306 at SDI. The rst
SCK rising edge loads the S/D bit. SDO transitions on the
falling edge of each SCK pulse.
Figures 8 and 9 are the transfer characteristics for the
bipolar and unipolar modes. Data is output at SDO in 2’s
complement format for bipolar readings or in straight
binary for unipolar readings.
Sleep Mode
The ADC enters sleep mode when CONVST is held high
after the conversion is complete (tCONV). The supply cur-
rent decreases to 7μA in sleep mode between conversions,
thereby reducing the average power dissipation as the
sample rate decreases. For example, the LTC2302/LTC2306
draw an average of 14μA with a 1ksps sampling rate. The
LTC2302/LTC2306 power down all circuitry when in sleep
mode.
Board Layout and Bypassing
To obtain the best performance, a printed circuit board with
a solid ground plane is required. Layout for the printed
circuit board should ensure digital and analog signal lines
are separated as much as possible. Care should be taken
not to run any digital signal alongside an analog signal.
All analog inputs should be shielded by GND. VREF and
VDD should be bypassed to the ground plane as close to
the pin as possible. Maintaining a low impedance path
for the common return of these bypass capacitors is
essential to the low noise operation of the ADC. These
traces should be as wide as possible. See Figure 5 for a
suggested layout.
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