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参数资料
| 型号： | DC1339A |
| 厂商： | Linear Technology |
| 文件页数： | 4/20页 |
| 文件大小： | 0K |
| 描述： | BOARD SAR ADC LTC2302 |
| 软件下载： | QuikEval System |
| 设计资源： | DC1339A Design File DC1339A Schematic |
| 标准包装： | 1 |
| 系列： | QuikEval™ |
| ADC 的数量： | 1 |
| 位数： | 12 |
| 采样率（每秒）： | 500k |
| 数据接口： | MICROWIRE?，串行，SPI? |
| 输入范围： | ±VREF/2 |
| 在以下条件下的电源（标准）： | 14mW @ 500kSPS |
| 已用 IC / 零件： | LTC2302 |
| 已供物品： | 板 |
| 相关产品： | LTC2302IDD#TRPBF-ND - IC ADC 12-BIT 1CH 500KSPS 10DFN LTC2302IDD#PBF-ND - IC ADC 12BIT 1CH 500KSPS 10-DFN LTC2302CDD#TRPBF-ND - IC ADC 12-BIT 1CH 500KSPS 10DFN LTC2302CDD#PBF-ND - IC ADC 12BIT 1CH 500KSPS 10-DFN |
LTC2302/LTC2306
12
23026fa
TIMING DIAGRAMS
tWLCLK (SCK Low Time)
tWHCLK (SCK High Time)
tHD (Hold Time SDI After SCK↑)
tSUDI (Setup Time SDI Stable Before SCK↑)
Voltage Waveforms for ten
Voltage Waveforms for SDO Rise and Fall Times tr, tf
APPLICATIONS INFORMATION
23026 TD03
SCK
SDI
tWLCLK
tWHCLK
tHD
tSUDI
23026 TD04
CONVST
SDO
ten
SDO
tr
tf
23004 TD05
VOH
VOL
Overview
The LTC2302/LTC2306 are low noise, 500ksps, 1-/2-
channel, 12-bit successive approximation register (SAR)
A/D converters. The LTC2306 includes a 2-channel analog
input multiplexer (MUX) while the LTC2302 includes an
input MUX that allows the polarity of the differential input
to be selected. Both ADCs include an SPI-compatible
serial port for easy data transfers and can operate in
either unipolar or bipolar mode. Unipolar mode should be
used for single-ended operation with the LTC2306, since
single-ended input signals are always referenced to GND.
The LTC2302/LTC2306 can be put into a power-down sleep
mode during idle periods to save power.
Conversions are initiated by a rising edge on the CONVST
input. Once a conversion cycle has begun, it cannot be
restarted. Between conversions, a 6-bit input word (DIN)
at the SDI input congures the MUX and programs vari-
ous modes of operation. As the DIN bits are shifted in,
data from the previous conversion is shifted out on SDO.
After the 6 bits of the DIN word have been shifted in, the
ADC begins acquiring the analog input in preparation for
the next conversion as the rest of the data is shifted out.
The acquire phase requires a minimum time of 240ns
for the sample-and-hold capacitors to acquire the analog
input signal.
During the conversion, the internal 12-bit capacitive
charge-redistribution DAC output is sequenced through a
successive approximation algorithm by the SAR starting
from the most signicant bit (MSB) to the least signicant
bit (LSB). The sampled input is successively compared
with binary weighted charges supplied by the capacitive
DAC using a differential comparator. At the end of a
conversion, the DAC output balances the analog input.
The SAR contents (a 12-bit data word) that represent the
sampled analog input are loaded into 12 output latches
that allow the data to be shifted out.
Programming the LTC2306 and LTC2302
The software compatible LTC2302/LTC2306/LTC2308 fam-
ily features a 6-bit DIN word to program various modes of
operation. Don’t care bits (X) are ignored. The SDI data
bits are loaded on the rising edge of SCK, with the S/D bit
loaded on the rst rising edge (see Figure 6 in the Timing
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