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参数资料
| 型号： | DC178A |
| 厂商： | Linear Technology |
| 文件页数： | 15/28页 |
| 文件大小： | 0K |
| 描述： | BOARD SAR ADC LTC1418 |
| 设计资源： | DC178A Design File DC178A Schematic |
| 标准包装： | 1 |
| ADC 的数量： | 1 |
| 位数： | 14 |
| 采样率（每秒）： | 200k |
| 数据接口： | 串行，并联 |
| 输入范围： | ±2.048 V |
| 已用 IC / 零件： | LTC1418 |
| 已供物品： | 板 |
| 相关产品： | LTC1418IG#PBF-ND - IC A/D CONV 14BIT SRL&PAR 28SSOP LTC1418AIG#TRPBF-ND - IC A/D CONV 14BIT SRL&PAR 28SSOP LTC1418CG#TRPBF-ND - IC A/D CONV 14BIT SRL&PAR 28SSOP LTC1418ACG#TRPBF-ND - IC A/D CONV 14BIT SRL&PAR 28SSOP LTC1418IG#TRPBF-ND - IC A/D CONV 14BIT SRL&PAR 28SSOP LTC1418CN#PBF-ND - IC A/D CONV 14BIT SRL&PAR 28-DIP LTC1418IN#PBF-ND - IC A/D CONV 14BIT SRL&PAR 28-DIP LTC1418CG#PBF-ND - IC A/D CONV 14BIT SRL&PAR 28SSOP LTC1418ACG#PBF-ND - IC A/D CONV 14BIT SRL&PAR 28SSOP LTC1418AIG#PBF-ND - IC A/D CONV 14BIT SRL&PAR 28SSOP 更多... |
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22
LTC1418
APPLICATIONS INFORMATION
WU
U
Figure 22. Internal Conversion Clock Selected. Data Transferred During Conversion Using
the ADC Clock Output as a Master Shift Clock (SCLK Driven from CLKOUT)
two zeros. The MSB (D13) will be valid on the first rising
and the first falling edge of the SCLK. D12 will be valid on
the second rising and the second falling edge as will all
the remaining bits. The data may be captured on either
edge. The largest hold time margin is achieved if data is
captured on the rising edge of SCLK.
BUSY gives the end of conversion indication. When the
LTC1418 is configured as a master serial device, BUSY
can be used as a framing pulse and to three-state the
t15
t14
SCLK
VIL
VOH
VOL
DOUT
1418 F21
Figure 21. SCLK to DOUT Delay
LTC1418
BUSY (= RD)
CLKOUT ( = SCLK)
BUSY
CONVST
RD
SCLK
CLKOUT
EXT/INT
DOUT
26
24
23
17
18
20
25
19
DOUT
CS
1418 F22a
P OR DSP
(CONFIGURED
AS SLAVE)
OR
SHIFT
REGISTER
D12
D11
D12
CAPTURE ON
RISING CLOCK
D13
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
FILL
ZEROS
D13
1
t5
t6
23456789
10
11
12
13
14
15
16
1
2
3
D13
D12
D11
Hi-Z
DATA N
DATA (N – 1)
(SAMPLE N)
(SAMPLE N + 1)
DOUT
CS = EXT/INT = 0
CLKOUT (= SCLK)
CONVST
t13
tCONV
t8
SAMPLE
HOLD
t10
t7
t11
1418 F22b
BUSY (= RD)
t15
t14
CLKOUT
(= SCLK)
VIL
VOH
VOL
DOUT
CAPTURE ON
FALLING CLOCK
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