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参数资料
| 型号： | DC178A |
| 厂商： | Linear Technology |
| 文件页数： | 17/28页 |
| 文件大小： | 0K |
| 描述： | BOARD SAR ADC LTC1418 |
| 设计资源： | DC178A Design File DC178A Schematic |
| 标准包装： | 1 |
| ADC 的数量： | 1 |
| 位数： | 14 |
| 采样率（每秒）： | 200k |
| 数据接口： | 串行，并联 |
| 输入范围： | ±2.048 V |
| 已用 IC / 零件： | LTC1418 |
| 已供物品： | 板 |
| 相关产品： | LTC1418IG#PBF-ND - IC A/D CONV 14BIT SRL&PAR 28SSOP LTC1418AIG#TRPBF-ND - IC A/D CONV 14BIT SRL&PAR 28SSOP LTC1418CG#TRPBF-ND - IC A/D CONV 14BIT SRL&PAR 28SSOP LTC1418ACG#TRPBF-ND - IC A/D CONV 14BIT SRL&PAR 28SSOP LTC1418IG#TRPBF-ND - IC A/D CONV 14BIT SRL&PAR 28SSOP LTC1418CN#PBF-ND - IC A/D CONV 14BIT SRL&PAR 28-DIP LTC1418IN#PBF-ND - IC A/D CONV 14BIT SRL&PAR 28-DIP LTC1418CG#PBF-ND - IC A/D CONV 14BIT SRL&PAR 28SSOP LTC1418ACG#PBF-ND - IC A/D CONV 14BIT SRL&PAR 28SSOP LTC1418AIG#PBF-ND - IC A/D CONV 14BIT SRL&PAR 28SSOP 更多... |
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24
LTC1418
APPLICATIONS INFORMATION
WU
U
clock to EXTCLKIN. The same clock is also applied to SCLK
to provide a data shift clock. To maintain accuracy the
conversion clock frequency must be between 30kHz and
4.5MHz.
It is not recommended to clock data with an external clock
during a conversion that is running on an internal clock
because the asynchronous clocks may create noise.
Serial Data Output After a Conversion
Using Internal Conversion Clock and External Data Clock.
In this mode, data is output after the end of each conver-
sion but before the next conversion is started (Figure 24).
The internal clock is used as the conversion clock and an
external clock is used for the SCLK. This mode is useful in
applications where the processor acts as a master serial
device. This mode is SPI and MICROWIRE compatible. It
LTC1418
BUSY
CONVST
26
24
19
20
25
23
17
CONVST
RD
SCLK
EXT/INT
DOUT
CS
1418 F24a
P OR DSP
INT
C0
SCK
MISO
12 11 10 987654321
0
FILL
ZEROS
D13
t5
t6
123456789 10 11 12 13 14 15 16
Hi-Z
DATA N
Hi-Z
(SAMPLE N)
DOUT
CS = EXT/INT = 0
CONVST
t13
tCONV
t8
HOLD
SAMPLE
t9
t10
1418 F24b
t11
BUSY
SCLK
RD
D11
D12
CAPTURE ON
RISING CLOCK
D13
t15
t14
tLSCLK
tHSCLK
SCLK
VIL
VOH
VOL
DOUT
CAPTURE ON
FALLING CLOCK
Figure 24. Internal Conversion Clock Selected. Data Transferred After Conversion
Using an External SCLK. BUSY
↑ Indicates End of Conversion
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