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参数资料
| 型号： | DC178A |
| 厂商： | Linear Technology |
| 文件页数： | 23/28页 |
| 文件大小： | 0K |
| 描述： | BOARD SAR ADC LTC1418 |
| 设计资源： | DC178A Design File DC178A Schematic |
| 标准包装： | 1 |
| ADC 的数量： | 1 |
| 位数： | 14 |
| 采样率（每秒）： | 200k |
| 数据接口： | 串行，并联 |
| 输入范围： | ±2.048 V |
| 已用 IC / 零件： | LTC1418 |
| 已供物品： | 板 |
| 相关产品： | LTC1418IG#PBF-ND - IC A/D CONV 14BIT SRL&PAR 28SSOP LTC1418AIG#TRPBF-ND - IC A/D CONV 14BIT SRL&PAR 28SSOP LTC1418CG#TRPBF-ND - IC A/D CONV 14BIT SRL&PAR 28SSOP LTC1418ACG#TRPBF-ND - IC A/D CONV 14BIT SRL&PAR 28SSOP LTC1418IG#TRPBF-ND - IC A/D CONV 14BIT SRL&PAR 28SSOP LTC1418CN#PBF-ND - IC A/D CONV 14BIT SRL&PAR 28-DIP LTC1418IN#PBF-ND - IC A/D CONV 14BIT SRL&PAR 28-DIP LTC1418CG#PBF-ND - IC A/D CONV 14BIT SRL&PAR 28SSOP LTC1418ACG#PBF-ND - IC A/D CONV 14BIT SRL&PAR 28SSOP LTC1418AIG#PBF-ND - IC A/D CONV 14BIT SRL&PAR 28SSOP 更多... |
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4
LTC1418
TI I G CHARACTERISTICS
W U
(Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
fSAMPLE(MAX)
Maximum Sampling Frequency
q
200
kHz
tCONV
Conversion Time
q
3.4
4
s
tACQ
Acquisition Time
q
0.3
1
s
tACQ + tCONV
Acquisition Plus Conversion Time
q
3.7
5
s
t1
CS to RD Setup Time
(Notes 9, 10)
q
0ns
t2
CS
↓ to CONVST↓ Setup Time
(Notes 9, 10)
q
40
ns
t3
CS
↓ to SHDN↓ Setup Time to Ensure Nap Mode
(Notes 9, 10)
q
40
ns
t4
SHDN
↑ to CONVST↓ Wake-Up Time from Nap Mode
(Note 10)
500
ns
t5
CONVST Low Time
(Notes 10, 11)
q
40
ns
t6
CONVST to BUSY Delay
CL = 25pF
q
35
70
ns
t7
Data Ready Before BUSY
↑
20
35
ns
q
15
ns
t8
Delay Between Conversions
(Note 10)
q
500
ns
t9
Wait Time RD
↓ After BUSY↑
q
–5
ns
t10
Data Access Time After RD
↓
CL = 25pF
15
30
ns
q
40
ns
CL = 100pF
20
40
ns
q
55
ns
t11
Bus Relinquish Time
820
ns
Commercial
q
25
ns
Industrial
q
30
ns
t12
RD Low Time
q
t10
ns
t13
CONVST High Time
40
ns
t14
Delay Time, SCLK
↓ to DOUT Valid
CL = 25pF (Note 9)
q
35
70
ns
t15
Time from Previous Data Remain Valid After SCLK
↓
CL = 25pF (Note 9)
q
15
25
ns
fSCLK
Shift Clock Frequency
(Notes 9, 10)
0
12.5
MHz
fEXTCLKIN
External Conversion Clock Frequency
(Notes 9, 10)
0.03
4.5
MHz
tdEXTCLKIN
Delay Time, CONVST
↓ to External Conversion Clock Input
(Notes 9, 10)
533
s
tH SCLK
SCLK High Time
(Notes 9, 10)
10
ns
tL SCLK
SCLK Low Time
(Notes 9, 10)
20
ns
tH EXTCLKIN
EXTCLKIN High Time
(Notes 9, 10)
250
ns
tL EXTCLKIN
EXTCLKIN Low Time
(Notes 9, 10)
250
ns
The q denotes specifications which apply over the full operating
temperature range; all other limits and typicals TA = 25°C.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with DGND and
AGND wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below VSS or above VDD, they
will be clamped by internal diodes. This product can handle input currents
greater than 100mA below VSS or above VCC without latchup.
Note 4: When these pin voltages are taken below VSS they will be clamped
by internal diodes. This product can handle input currents greater than
100mA below VSS without latchup. These pins are not clamped to VDD.
Note 5: VDD = 5V, VSS = 0V or – 5V, fSAMPLE = 200kHz, tr = tf = 5ns unless
otherwise specified.
Note 6: Linearity, offset and full-scale specifications apply for a single-
ended input with AIN
– grounded.
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: Bipolar offset is the offset voltage measured from – 0.5LSB
when the output code flickers between 0000 0000 0000 00 and
1111 1111 1111 11.
Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.
Note 11: The falling edge of CONVST starts a conversion. If CONVST
returns high at a critical point during the conversion, it can create small
errors. For best performance ensure that CONVST returns high either
within 2.1
s after the conversion starts or after BUSY rises.
Note 12: Pins 16 (D4/EXTCLKIN), 17 (D3/SCLK) and 20 (DO/EXT/INT) at
0V or 5V. See Power Shutdown.
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