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| 型号： | DC571A |
| 厂商： | Linear Technology |
| 文件页数： | 10/48页 |
| 文件大小： | 0K |
| 描述： | BOARD DELTA SIGMA ADC LTC2418 |
| 软件下载： | QuikEval System |
| 设计资源： | DC571A Design File DC571A Schematic |
| 标准包装： | 1 |
| 系列： | QuikEval™ |
| ADC 的数量： | 1 |
| 位数： | 24 |
| 采样率（每秒）： | 7.5 |
| 数据接口： | MICROWIRE?，串行，SPI? |
| 工作温度： | 0°C ~ 70°C |
| 已用 IC / 零件： | LTC2418 |
| 已供物品： | 板 |
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LTC2414/LTC2418
18
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Table 5. LTC2414/LTC2418 State Duration
State
Operating Mode
Duration
CONVERT
Internal Oscillator
FO = LOW
133ms, Output Data Rate
≤ 7.5 Readings/s
(60Hz Rejection)
FO = HIGH
160ms, Output Data Rate
≤ 6.2 Readings/s
(50Hz Rejection)
External Oscillator
FO = External Oscillator
20510/fEOSCs, Output Data Rate ≤ fEOSC/20510 Readings/s
with Frequency fEOSC kHz
(fEOSC/2560 Rejection)
SLEEP
As Long As CS = HIGH Until CS = LOW and SCK
DATA OUTPUT
Internal Serial Clock
FO = LOW/HIGH
As Long As CS = LOW But Not Longer Than 1.67ms
(Internal Oscillator)
(32 SCK cycles)
FO = External Oscillator with
As Long As CS = LOW But Not Longer Than 256/fEOSCms
Frequency fEOSC kHz
(32 SCK cycles)
External Serial Clock with
As Long As CS = LOW But Not Longer Than 32/fSCKms
Frequency fSCK kHz
(32 SCK cycles)
Serial Clock Input/Output (SCK)
The serial clock signal present on SCK (Pin 18) is used to
synchronize the data transfer. Each bit of data is shifted out
the SDO pin on the falling edge of the serial clock and each
input bit is shifted in the SDI pin on the rising edge of the
serial clock.
In the Internal SCK mode of operation, the SCK pin is an
output and the LTC2414/LTC2418 create their own serial
clock by dividing the internal conversion clock by 8. In the
External SCK mode of operation, the SCK pin is used as
input. The internal or external SCK mode is selected on
power-up and then reselected every time a HIGH-to-LOW
transition is detected at the CS pin. If SCK is HIGH or float-
ing at power-up or during this transition, the converter
enters the internal SCK mode. If SCK is LOW at power-up
or during this transition, the converter enters the external
SCK mode.
Serial Data Input (SDI)
The serial data input pin, SDI (Pin 20), is used to shift in the
channel control bits during the data output state to prepare
the channel selection for the following conversion.
When CS (Pin 16) is HIGH or the converter is in the con-
version state, the SDI input is ignored and may be driven
HIGH or LOW. When CS goes LOW and the conversion is
complete, SDO goes low and then SDI starts to shift in bits
on the rising edge of SCK.
Serial Data Output (SDO)
The serial data output pin, SDO (Pin 17), provides the
result of the last conversion as a serial bit stream (MSB
first) during the data output state. In addition, the SDO pin
is used as an end of conversion indicator during the
conversion and sleep states.
When CS (Pin 16) is HIGH, the SDO driver is switched to
a high impedance state. This allows sharing the serial
interface with other devices. If CS is LOW during the
convert or sleep state, SDO will output EOC. If CS is LOW
during the conversion phase, the EOC bit appears HIGH on
the SDO pin. Once the conversion is complete, EOC goes
LOW. The device remains in the sleep state until the first
rising edge of SCK occurs while CS = LOW.
Chip Select Input (CS)
The active LOW chip select, CS (Pin 16), is used to test the
conversion status and to enable the data input/output
transfer as described in the previous sections.
In addition, the CS signal can be used to trigger a new
conversion cycle before the entire serial data transfer has
been completed. The LTC2414/LTC2418 will abort any
serial data transfer in progress and start a new conversion
cycle anytime a LOW-to-HIGH transition is detected at the
CS pin after the converter has entered the data input/
output state (i.e., after the first rising edge of SCK occurs
with CS = LOW). If the device has not finished loading the
APPLICATIO S I FOR ATIO
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