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参数资料
| 型号： | DC571A |
| 厂商： | Linear Technology |
| 文件页数： | 8/48页 |
| 文件大小： | 0K |
| 描述： | BOARD DELTA SIGMA ADC LTC2418 |
| 软件下载： | QuikEval System |
| 设计资源： | DC571A Design File DC571A Schematic |
| 标准包装： | 1 |
| 系列： | QuikEval™ |
| ADC 的数量： | 1 |
| 位数： | 24 |
| 采样率（每秒）： | 7.5 |
| 数据接口： | MICROWIRE?，串行，SPI? |
| 工作温度： | 0°C ~ 70°C |
| 已用 IC / 零件： | LTC2418 |
| 已供物品： | 板 |
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LTC2414/LTC2418
16
241418fa
parity bit representing the parity of the previous 31 bits. The
parity bit is useful to check the output data integrity espe-
cially when the output data is transmitted over a distance.
The third and fourth bits together are also used to indicate
an underrange condition (the differential input voltage is be-
low – FS) or an overrange condition (the differential input
voltage is above + FS).
Bit 31 (first output bit) is the end of conversion (EOC)
indicator. This bit is available at the SDO pin during the
conversion and sleep states whenever the CS pin is LOW.
This bit is HIGH during the conversion and goes LOW
when the conversion is complete.
Bit 30 (second output bit) is a dummy bit (DMY) and is
always LOW.
Bit 29 (third output bit) is the conversion result sign indi-
cator (SIG). If VIN is >0, this bit is HIGH. If VIN is <0, this
bit is LOW.
Bit 28 (fourth output bit) is the most significant bit (MSB)
of the result. This bit in conjunction with Bit 29 also
provides the underrange or overrange indication. If both
Bit 29 and Bit 28 are HIGH, the differential input voltage is
above +FS. If both Bit 29 and Bit 28 are LOW, the
differential input voltage is below –FS.
The function of these bits is summarized in Table 3.
Table 3. LTC2414/LTC2418 Status Bits
Bit 31
Bit 30 Bit 29 Bit 28
Input Range
EOC
DMY
SIG
MSB
VIN ≥ 0.5 VREF
00
1
0V
≤ VIN < 0.5 VREF
00
1
0
–0.5 VREF ≤ VIN < 0V
0
1
VIN < – 0.5 VREF
00
0
Bits 28-6 are the 23-bit conversion result MSB first.
Bit 6 is the least significant bit (LSB).
Bits 5-1 are the corresponding channel selection bits for
the present conversion result with bit SGL output first as
shown in Figure 3.
Bit 0 is the parity bit representing the parity of the previous
31 bits. Including the parity bit, the total numbers of 1’s
and 0’s in the output data are always even.
Data is shifted out of the SDO pin under control of the serial
clock (SCK), see Figure 3. Whenever CS is HIGH, SDO
remains high impedance and any externally generated
SCK clock pulses are ignored by the internal data out shift
register.
In order to shift the conversion result out of the device, CS
must first be driven LOW. EOC is seen at the SDO pin of the
device once CS is pulled LOW. EOC changes real time from
HIGH to LOW at the completion of a conversion. This
signal may be used as an interrupt for an external micro-
controller. Bit 31 (EOC) can be captured on the first rising
edge of SCK. Bit 30 is shifted out of the device on the first
falling edge of SCK. The final data bit (Bit 0) is shifted out
on the falling edge of the 31st SCK and may be latched on
the rising edge of the 32nd SCK pulse. On the falling edge
of the 32nd SCK pulse, SDO goes HIGH indicating the
initiation of a new conversion cycle. This bit serves as EOC
(Bit 31) for the next conversion cycle. Table 4 summarizes
the output data format.
As long as the voltage applied to any channel (CH0-CH15,
COM) is maintained within the – 0.3V to (VCC + 0.3V)
absolute maximum operating range, a conversion result is
generated for any differential input voltage VIN from
–FS = – 0.5 VREF to +FS = 0.5 VREF. For differential input
voltages greater than +FS, the conversion result is clamped
to the value corresponding to the +FS + 1LSB. For differ-
ential input voltages below –FS, the conversion result is
clamped to the value corresponding to –FS – 1LSB.
Frequency Rejection Selection (FO)
The LTC2414/LTC2418 internal oscillator provides better
than 110dB normal mode rejection at the line frequency
and all its harmonics for 50Hz
±2% or 60Hz ±2%. For
60Hz rejection, FO should be connected to GND while for
50Hz rejection the FO pin should be connected to VCC.
The selection of 50Hz or 60Hz rejection can also be made
by driving FO to an appropriate logic level. A selection
change during the sleep or data output states will not
disturb the converter operation. If the selection is made
during the conversion state, the result of the conversion in
progress may be outside specifications but the following
conversions will not be affected.
APPLICATIO S I FOR ATIO
WU
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