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| 型号： | DC571A |
| 厂商： | Linear Technology |
| 文件页数： | 19/48页 |
| 文件大小： | 0K |
| 描述： | BOARD DELTA SIGMA ADC LTC2418 |
| 软件下载： | QuikEval System |
| 设计资源： | DC571A Design File DC571A Schematic |
| 标准包装： | 1 |
| 系列： | QuikEval™ |
| ADC 的数量： | 1 |
| 位数： | 24 |
| 采样率（每秒）： | 7.5 |
| 数据接口： | MICROWIRE?，串行，SPI? |
| 工作温度： | 0°C ~ 70°C |
| 已用 IC / 零件： | LTC2418 |
| 已供物品： | 板 |
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LTC2414/LTC2418
26
241418fa
Input Current
If complete settling occurs on the input, conversion re-
sults will be unaffected by the dynamic input current. An
incomplete settling of the input signal sampling process
may result in gain and offset errors, but it will not degrade
the INL performance of the converter. Figure 11 shows the
mathematical expressions for the average bias currents
flowing through the IN+ and IN– pins as a result of the
sampling charge transfers when integrated over a sub-
stantial time period (longer than 64 internal clock cycles).
The effect of this input dynamic current can be analyzed
using the test circuit of Figure 12. The CPAR capacitor
includes the LTC2414/LTC2418 pin capacitance (5pF typi-
cal) plus the capacitance of the test fixture used to obtain
the results shown in Figures 13 and 14. A careful imple-
mentation can bring the total input capacitance (CIN +
CPAR) closer to 5pF thus achieving better performance
than the one predicted by Figures 13 and 14. For simplic-
ity, two distinct situations can be considered.
For relatively small values of input capacitance (CIN <
0.01
F), the voltage on the sampling capacitor settles
almost completely and relatively large values for the
APPLICATIO S I FOR ATIO
WU
UU
source impedance result in only small errors. Such values
for CIN will deteriorate the converter offset and gain
performance without significant benefits of signal filtering
and the user is advised to avoid them. Nevertheless, when
small values of CIN are unavoidably present as parasitics
of input multiplexers, wires, connectors or sensors, the
LTC2414/LTC2418 can maintain its exceptional accuracy
while operating with relative large values of source resis-
tance as shown in Figures 13 and 14. These measured
results may be slightly different from the first order
approximation suggested earlier because they include the
effect of the actual second order input network together
with the nonlinear settling process of the input amplifiers.
For small CIN values, the settling on IN+ and IN– occurs
almost independently and there is little benefit in trying to
match the source impedance for the two pins.
Larger values of input capacitors (CIN > 0.01F) may be
required in certain configurations for antialiasing or gen-
eral input signal filtering. Such capacitors will average the
input sampling charge and the external source resistance
will see a quasi constant input differential impedance.
When FO = LOW (internal oscillator and 60Hz notch), the
VREF+
VIN+
VCC
RSW (TYP)
20k
ILEAK
VCC
ILEAK
VCC
RSW (TYP)
20k
CEQ
18pF
(TYP)
RSW (TYP)
20k
ILEAK
IIN+
VIN–
IIN–
IREF+
IREF–
2414/18 F11
ILEAK
VCC
ILEAK
SWITCHING FREQUENCY
fSW = 76800Hz INTERNAL OSCILLATOR (FO = LOW OR HIGH)
fSW = 0.5 fEOSC EXTERNAL OSCILLATOR
VREF–
RSW (TYP)
20k
Figure 11. LTC2414/LTC2418 Equivalent Analog Input Circuit
IIN
VV
V
R
IIN
VV
V
R
I REF
VV
V
R
V
VR
I REF
VV
V
R
V
VR
where
AVG
IN
INCM
REFCM
EQ
AVG
IN
INCM
REFCM
EQ
AVG
REF
INCM
REFCM
EQ
IN
REF
EQ
AVG
REF
INCM
REFCM
EQ
IN
REF
EQ
+
+
() = +
() = +
() = +
() = +
+
05
15
05
15
05
2
.
::
.
./
V
REF
V
REF
VIN
IN
V
IN
R
M
INTERNAL OSCILLATOR
Hz Notch F
LOW
R
M
INTERNAL OSCILLATOR
Hz Notch F
HIGH
R
f
EXTERNAL OSCILLATOR
REF
REFCM
IN
INCM
EQ
O
EQ
O
EQ
EOSC
=
=
+
=
=
==
()
==
()
=
()
+
+
+
+
2
361
60
432
50
0 555 1012
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