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参数资料
| 型号： | DR-TRC101-315-DK |
| 厂商： | RFM |
| 文件页数： | 16/42页 |
| 文件大小： | 0K |
| 描述： | RFIC TRANCEIVER DEVELOPMENT KIT |
| 产品变化通告： | RFIC Obsolescence 15/Sept/2009 |
| 标准包装： | 1 |
| 类型： | 收发器，SRR |
| 频率： | 315MHz |
| 适用于相关产品： | TRC101-315 |
| 已供物品： | 2 个板，2 根天线，电池，线缆，CD |
| 其它名称： | 583-1051 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页当前第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页
Configuration Register [POR=8008h]
Bit
15
1
Bit
14
0
Bit
13
0
Bit
12
0
Bit
11
0
Bit
10
0
Bit
9
0
Bit
8
0
Bit
7
DATEN
Bit
6
FIFEN
Bit
5
BAND1
Bit
4
BAND0
Bit
3
CAP3
Bit
2
CAP2
Bit
1
CAP1
Bit
0
CAP0
The configuration register sets up the following:
?
?
?
?
Internal Data Register
Internal FIFO
Frequency Band in use
Crystal Load capacitance
Bit [15..8] – Command Code : These bits are the command code that is sent serially to the processor
that identifies the bits to be written to the configuration register.
Bit [7] – TX Data Register Enable : This bit enables the internal TX data register when set. If the internal
TX data register is used, the DATA/nFSEL pin (6) must be pulled “High”.
Bit [6] – FIFO Enable : This bit enables the internal data FIFO when set. If the data FIFO is enabled, the
DATA/nFSEL pin (6) must be pulled “Low”. The FIFO is used to store data during receive. If the FIFO is
disabled by clearing this bit, pin 6 (Data) and pin 7 (Recovered Clock) are used to receive data.
Bit [5..4] – Band Select : These bits set the frequency band to be used. There are four (4) bands that are
supported. See Table 3 below for Band configuration.
TABLE 3.
Frequency Band BAND1
315 0
433 0
868 1
916 1
BAND0
0
1
0
1
Bit [3..0] – Load Capacitance Select : These bits set the load capacitance for the crystal reference. The
internal load capacitance can be varied from 8.5pF to 16pF in 0.5pF steps to accommodate a wide range
of crystal vendors as well as adjust the reference frequency and compensate for stray capacitance that
may be introduced due to PCB layout. See Table 4 below for load capacitance configuration.
TABLE 4.
CAP3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
CAP2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
CAP1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
CAP0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Crystal Load
Capacitance
8.5
9
9.5
10
10.5
11
11.5
12
12.5
13
13.5
14
14.5
15
15.5
16
www.RFM.com
Email: info@rfm.com
Page 16 of 42
?by RF Monolithics, Inc.
TRC101 - 4/8/08
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