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参数资料
| 型号： | DR-TRC101-315-DK |
| 厂商： | RFM |
| 文件页数： | 8/42页 |
| 文件大小： | 0K |
| 描述： | RFIC TRANCEIVER DEVELOPMENT KIT |
| 产品变化通告： | RFIC Obsolescence 15/Sept/2009 |
| 标准包装： | 1 |
| 类型： | 收发器，SRR |
| 频率： | 315MHz |
| 适用于相关产品： | TRC101-315 |
| 已供物品： | 2 个板，2 根天线，电池，线缆，CD |
| 其它名称： | 583-1051 |
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The receive data rate is programmable from 337bps to 256kbps. An internal prescaler is used to give
better resolution when setting up the receive data rate. The prescaler is optional and may be disabled
through the Data Rate Setup Register .
The type of baseband filtering is selectable between an Analog filter and a Digital filter. The analog filter
is a simple RC lowpass filter. An external capacitor may be chosen depending on the actual data rate.
The chip has an integrated 10K Ohm resistor in series that makes the RC lowpass network. With the
analog filter selected, a maximum data rate of 256kbps can be achieved. The digital filter is used with a
clock frequency of 29X data rate. In this mode a clock recovery (CR) circuit is used to provide for a
synchronized clock source to recover the data using an external processor. The CR has three modes of
operation: fast, slow, and automatic, all configurable through the Baseband Filter Register . The CR
circuit works by sampling the preamble on the incoming data. The preamble must contain a series of 1’s
and 0’s in order for the CR circuit to properly extract the data timing. In slow mode the CR circuit requires
more sampling (12 to 16 bits) and thus has a longer settling time before locking. In fast mode the CR
circuit takes fewer samples (6 to 8 bits) before locking so settling time is not as long and timing accuracy
is not critical. In automatic mode the CR circuit begins in fast mode to coarsely acquire the timing period
with fewer samples and then changes to slow mode after locking. Further details of the CR and data rate
clock are provided in the Baseband Filter Register . CR is only used with the digital filter and data rate
clock. These are not used when configured for the analog filter.
Transmit Register
The transmit register is configured as two 8-bit shift registers connected in series to form a single 16-bit
shift register. On POR the registers are filled with the value AAh. This can be used to generate a
preamble before sending actual data, however, the value is not reloaded when the transmit register is re-
enabled. When the transmitter is enabled through the Power Management Register , transmission begins
immediately and the value in the transmit register begins to be sent out. If there is nothing written to the
register then it will send out the default value AAh. The next data byte can be loaded via the SPI bus to
the transmit register by monitoring the SDO pin for a logic ‘1’ or waiting for an interrupt from the nIRQ pin.
After data has been loaded to the transmit register the processor must wait for the next interrupt before
disabling the transmitter or the rest of the data left in the register will be lost. Inserting a dummy byte of
all 0’s is recommended for the last byte of data loaded.
Receive FIFO
The receive FIFO is configured as one 16-bit register. The FIFO can be configured to generate an
interrupt after a predefined number of bits have been received. This threshold is programmable from 1 to
16 bits (0..15). It is recommended to set the threshold to at least half the length of the register (8 bits) to
insure the external host processor has time to set up before performing a FIFO read. The FIFO read
clock (SCK) must be < f XTAL /4 or <2.5 MHz for a 10 MHz reference xtal.
The receive FIFO may also be configured to fill only when valid data has been identified. The RXC101
has a synchronous pattern detector that watches incoming data for a particular pattern. When it sees this
pattern it begins to store any data that follows. At the same time, if pin 16 is configured for Valid Data
Indicator output (See Receiver Control Register) , this pin will go ‘high’ signaling valid data. This can be
used to wake up or prepare a host processor for processing data. The internal synchronous pattern is set
to 2DD4h and is not configurable.
The receive packet structure when using the synchronous pattern should be:
PREAMBLE 0xAA
PREAMBLE 0xAA
SYNCH BYTE 0x2D
SYNCH BYTE 0XD4
DATA [N]
DATA [N+1]
DATA [N+2
Any packet sent, whether using the synchronous pattern or not, should always start with a preamble
sequence of alternating 1’s and 0’s, such as 1-0-1-0-1. This corresponds to sending a 0xAA or 0x55.
The preamble may be one byte (Fast CR lock) or two bytes (Slow CR lock). The next two bytes should be
the synchronous pattern. In this case, data storage begins immediately following the 2 nd synch byte. All
other following bytes are treated as data.
www.RFM.com
Email: info@rfm.com
Page 8 of 42
?by RF Monolithics, Inc.
TRC101 - 4/8/08
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