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参数资料
| 型号： | DR-TRC101-315-DK |
| 厂商： | RFM |
| 文件页数： | 17/42页 |
| 文件大小： | 0K |
| 描述： | RFIC TRANCEIVER DEVELOPMENT KIT |
| 产品变化通告： | RFIC Obsolescence 15/Sept/2009 |
| 标准包装： | 1 |
| 类型： | 收发器，SRR |
| 频率： | 315MHz |
| 适用于相关产品： | TRC101-315 |
| 已供物品： | 2 个板，2 根天线，电池，线缆，CD |
| 其它名称： | 583-1051 |
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Automatic Frequency Adjust Register [POR=C4F7h]
Bit
15
1
Bit
14
1
Bit
13
0
Bit
12
0
Bit
11
0
Bit
10
1
Bit
9
0
Bit
8
0
Bit
7
AUTO1
Bit
6
AUTO0
Bit
5
RNG1
Bit
4
RNG0
Bit
3
STRB
Bit
2
ACCF
Bit
1
OFFEN
Bit
0
AFEN
The AFA (Automatic Frequency Adjust) Register configures:
?
?
?
Manual or Automatic frequency offset adjustment
Calculation of the offset value and write to the Status Register
Fine offset adjustment control
The AFA (Automatic Frequency Adjust) Register controls and configures the frequency adjustment range
and mode for keeping the transmitter and receiver frequency locked, providing for an optimal link. The
AFA may be manually controlled by an external processor by asserting a strobe signal to initiate a
sample, or may be setup for automatic operation, which uses the Valid Data Detector (VDI) signal to
initiate a frequency adjustment. When the VDI goes active, the AFA circuit performs a sample and
updates the offset register automatically. The elapsed time for an AFA is determined by the setting of the
clock recovery (CR) bit in the Baseband Filter Register . The AFA also calculates the offset of the transmit
and receive frequency. This offset value is included in the status register read and the AFA must be
disabled during the status read to ensure reporting good offset accuracy.
Bit [15..8] - Command Code : These bits are the command code that is sent serially to the processor that
identifies the bits to be written to the Automatic Frequency Adjust Register.
Bit [7..6] – Mode Selection : These bits select Automatic or Manual operation. When set to Manual
operation, the TRC101 will take a sample when a strobe signal (See Bit [3]) is written to the register.
There are four modes of operation. See Table 5 below for configuration.
TABLE 5.
Automatic fOFFSET
Mode
Mode Off
Run Once after Pwr-up
Keep offset during Rcv
ONLY
Keep offset indep of
VDI state
AUTO1
0
0
1
1
AUTO0
0
1
0
1
Mode(0,1) – The circuit takes a measurement only once after power-up.
Mode(1,0) – When the Valid Data Detector (VDI) pin is low, indicating poor receiving conditions,
the offset register is automatically cleared. Use this setting when receiving from several different
transmitters that are operating very close to the same frequencies so that the receiver may align
itself on each transmission from a different transmitter.
Mode(1,1) – This setting is best used when receiving from a single transmitter. The measured
offset value is kept independent of the state of the VDI signal. Once the link is aligned it may be
manually toggled by the user.
www.RFM.com
Email: info@rfm.com
Page 17 of 42
?by RF Monolithics, Inc.
TRC101 - 4/8/08
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