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| 型号： | DR-TRC103-915-EV |
| 厂商： | RFM |
| 文件页数： | 53/65页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION 915MHZ RFM RFIC |
| 标准包装： | 1 |
| 类型： | 收发器，SRR |
| 频率： | 902MHz ~ 928MHz |
| 适用于相关产品： | TRC103-915 |
| 已供物品： | 2 个板，天线，电池 |
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programming task less time critical. The values of P, S and R for OOK receive operation on several common
frequencies are given in Table 68 for a 0.1 MHz F IF2 . Software for determining P, S and R values for any in-band
frequency is provided with the TRC103 development kit.
Configuration
MCFG00 bits 4..3
P
S
R
868.3 MHz
10
85
63
107
915.0 MHz
01
121
1
143
955.0 MHz
10
126
26
143
Table 68
The RF channel frequency for OOK transmit is:
F RXRF = (14.4*(75*(P + 1) + S)/(R + 1)) - F IF2 , with P, S in the range 0 to 255, R in the range of 64 to 169
Where F RXRF and the OOK 2 nd IF frequency F IF2 are in MHz, and P, S, and R are divider integers where S must be
less than (P+1), and R has a value in the range of 64 to 169. An F IF2 value of 0.1 MHz is normally used. The val-
ues of P, S and R for OOK transmit operation on several common frequencies are given in Table 69 for a 0.1
MHz F IF2 . Software for determining P, S and R values is provided with the TRC103 development kit.
Configuration
MCFG00 bits 4..3
P
S
R
868.3 MHz
10
85
63
107
915.0 MHz
01
121
1
143
955.0 MHz
10
126
26
143
Table 69
6.6 TRC103 Data Mode Selection and Configuration
The TRC103 supports three data modes: continuous, buffered and packet. Continuous data mode provides the
most formatting flexibility, but places the heaviest demand on host microcontroller resources and requires the
most custom firmware development. In contrast, the Packet data mode unloads the host processor and the appli-
cation firmware from handing tasks such as DC-balanced data encoding, packet frame assembly and disassem-
bly, error detection, packet filtering and FIFO buffering. The trade-off for Packet data mode is limited flexibility in
data formatting parameters such as packet frame design. Buffered data mode falls between packet and Continu-
ous data mode capabilities, providing FIFO buffering, but allowing considerable flexibility in the design of the
packet frame.
Packet data mode is generally preferred as it supports the fastest application development time and requires the
smallest and least expensive host microcontroller. Buffered data mode covers applications that require a specific
packet frame design to support features such as multi-hop routing. Continuous data mode is reserved for special-
ized requirements, such as compatibility with a legacy product.
MCFG01 bit 5 and bit 2 select the data mode. Setting bit 2 to 1 enables packet mode regardless of the state of bit
5. If bit 2 is set to 0, then buffered mode is selected if bit 5 is set to 1 and continuous mode is selected if bit 5 is
set to 0. The TRC103 configuration details for each data mode are discussed below.
6.6.1 Continuous Data Mode
In Continuous data mode operation, transmitted data streams are applied to DATA Pin 20, and received data
streams are output on Pin 20. IRQ1 Pin 22 is usually configured to supply a clock signal to the host micro-
controller to pace the transmitted and received data steams. The clock signal is generated at the configured bit
rate. When transmitting, bits are clocked into Pin 20 on the low-to-high clock transitions at Pin 22.
www.RFM.com E-mail: info@rfm.com
? 2009-2010 by RF Monolithics, Inc.
Technical support +1.800.704.6079
Page 53 of 65
TRC103 - 11/29/12
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