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参数资料
| 型号： | DR-TRC105-304-EV |
| 厂商： | RFM |
| 文件页数： | 56/67页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION 304MHZ RFM RFIC |
| 标准包装： | 1 |
| 类型： | 收发器 |
| 频率： | 303.325MHz ~ 307.3MHz |
| 适用于相关产品： | TRC105 |
| 已供物品： | 2 个板，天线，电池 |
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Received bits are valid (clocked out) on Pin 20 on low-to-high clock transitions on Pin 22. The clock signal is con-
trolled by RXCFG12 bit 6. Setting this bit to 0 enables bit clocking and setting this bit to 1 disables bit clocking.
Clocking must be used for FSK transmissions. It is optional for OOK transmissions.
While clocking is optional for FSK and OOK reception, enabling clocking provides additional bit stream filtering
and regeneration, even if the clock signal is not used by the microcontroller. To effectively use the data and clock
recovery feature, data must be transmitted with a bit rate accuracy of better than ±2%, and a 1-0-1- 0… training
preamble of at least 24 bits must be sent at the beginning of a transmission. When clocking is enabled, continu-
ous mode will optionally support the detection of a start-of-packet (start) pattern when receiving. The start pattern
must be generated by the host microcontroller when transmitting. Start pattern detection is enabled by setting
RXCFG12 bit 5 to 1. The length of the start pattern is set by RXCFG12 bits 4..3 as follows:
RXCFG12 bits 4..3
00
01
10
11
Pattern Length
8 bits
16 bits
24 bits
32 bits
Table 75
The number of allowed bit errors in the start pattern is configured by RXCFG12 bits 2..1 as follows:
RXCFG12 bits 2..1
00
01
10
11
Error Tolerance
none
1 bit
2 bits
3 bits
Table 76
For most applications, a start pattern length of 24 to 32 bits is recommended with the error tolerance set to none.
The start pattern is stored in registers SYNCFG16 through SYNCFG19 . Received bits flow through a shift register
for pattern comparison with the most significant bit of SYNCFG16 compared to the earliest received bit and the
least significant bit of the last register (selected by the pattern length) compared to the last received bit. Pattern
detection is usually output on IRQ0, as discussed below. Refer to Figure 9 for pattern detection output timing. A
well designed pattern should contain approximately the same number of 1 and 0 bits to achieve DC-balance, it
should include frequent bit transitions, and it should be a pattern that is unlikely to occur in the encoded data fol-
lowing it.
As shown in Figure 19, two interrupt (control) outputs, IRQ0 and IRQ1, are provided by the TRC105 to coordinate
data flow to and from the host microcontroller. In Continuous data mode, one of two signals can be mapped to
IRQ0. This mapping is configured in register IRQCFG0D . Bits 7..6 select the signal for IRQ0 in the receive mode.
The mapping options for Continuous data mode are summarized in Table 77 , where X denotes a don’t care bit
value. Note that IRQ1 always outputs DCLK in Continuous data mode when clocking is enabled.
www.RFM.com E-mail: info@rfm.com
? 2009-2013 by RF Monolithics, Inc.
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Page 56 of 67
TRC105 - 05/29/13
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| DR-TRC105-315-DK | 功能描述:射频开发工具 TRC105 Development Kit 310-319 MHz RoHS:否 制造商:Taiyo Yuden 产品:Wireless Modules 类型:Wireless Audio 工具用于评估:WYSAAVDX7 频率: 工作电源电压:3.4 V to 5.5 V |
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